IP Library Granted Patent US 9,099,311
Granted Patent B2
US 9,099,311 · App. 13/756,412 · Granted Aug 4, 2015

Double stepped semiconductor substrate

Inventors: Meng-Ku Chen (New Taipei, TW); Hung-Ta Lin (Hsinchu, TW); Huicheng Chang (Tainan, TW)
Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
H01L21/02658H01L21/0243H01L21/02381H01L21/02538H01L21/02639H01L29/267
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Quick Facts
Patent No.
US 9,099,311
App. No.
13/756,412
Granted
Aug 4, 2015
Kind
B2
Abstract

A method for forming a double step surface on a semiconductor substrate includes, with an etching process used in a Metal-Organic Chemical Vapor Deposition (MOCVD) process, forming a rough surface on a region of a semiconductor substrate. The method further includes, with an annealing process used in the MOCVD process, forming double stepped surface on the region of the semiconductor substrate.

Claims (28)

1. A method for forming a double step surface on a semiconductor substrate, the method comprising:

with an etching process used in a Metal-Organic Chemical Vapor Deposition (MOCVD) process, forming a rough surface on a region of a semiconductor substrate, wherein the region includes a group IV semiconductor material;

with an annealing process used in the MOCVD process, forming a double stepped surface layer on the region of the semiconductor substrate; and

forming a group III-V semiconductor material layer on the double stepped surface layer, wherein the group III-V semiconductor material layer includes a group III semiconductor material and a group V semiconductor material, wherein after forming the group III-V semiconductor material layer the double stepped surface layer includes a first component of the group IV semiconductor material double bonded to a second component of the group IV semiconductor material and the group III semiconductor material doubled bonded to the group V semiconductor material, wherein the double stepped surface layer is free of the group IV semiconductor material being double bonded to the group V semiconductor material after forming the III-V group semiconductor material layer on the double stepped surface layer.

2. The method of claim 1 , wherein the group IV semiconductor material includes Si.

3. The method of claim 1 , wherein the group III semiconductor material includes Ga and the group V semiconductor material includes As.

4. The method of claim 3 , wherein the double stepped surface layer is free of anti-phase boundary (APB) defects.

5. The method of claim 1 , wherein the etching process includes a Hydrogen Chloride (HCl) etching process.

6. The method of claim 1 , wherein the formation of the double stepped surface layer is performed in a same chamber as the MOCVD process.

7. The method of claim 1 , wherein the first component of the group IV semiconductor material is Si and the second component of the group IV is Si.

8. The method of claim 1 , wherein the annealing process occurs at a temperature of about 1200° C.

9. A method for forming a double step surface on a semiconductor substrate, the method comprising:

with an etching process used in a Metal-Organic Chemical Vapor Deposition (MOCVD) process, forming a rough surface on a region of a semiconductor substrate, wherein the region includes a group IV semiconductor material;

with an annealing process used in the MOCVD process, forming a double stepped surface layer on the region of the semiconductor substrate; and

forming a group III-V semiconductor material layer onto the double stepped surface layer with the MOCVD process, wherein the group III-V semiconductor material layer includes a group III semiconductor material and a group V semiconductor material, wherein after forming the group III-V semiconductor material layer the double stepped surface layer includes a first component of the group IV semiconductor material double bonded to a second component of the group IV semiconductor material and the group III semiconductor material doubled bonded to the group V semiconductor material, wherein the double stepped surface layer is free of the group IV semiconductor material being double bonded to the group V semiconductor material after forming the III-V group semiconductor material layer on the double stepped surface layer;

wherein the double stepped region is such that there are fewer anti-phase boundary (APB) defects formed into the III-V semiconductor layer.

10. The method of claim 9 wherein the group IV semiconductor material includes Si.

11. The method of claim 9 , wherein the formation of the double stepped surface layer is performed in the same chamber as the MOCVD process.

12. The method of claim 9 , wherein the first component of the group IV semiconductor material is Si and the second component of the group IV is Si.

13. The method of claim 9 , wherein the annealing process occurs at a temperature of about 1200° C.

14. A method for forming a multi-step surface on a semiconductor substrate, the method comprising:

with an etching process used in a Metal-Organic Chemical Vapor Deposition (MOCVD) process, forming a first surface on a region of a semiconductor substrate; and

with an annealing process used in the MOCVD process, forming the multi-step surface on the region of the semiconductor substrate, wherein the annealing process occurs at a temperature of about 1200° C.

15. The method of claim 14 , wherein the semiconductor substrate includes a group IV semiconductor material.

16. The method of claim 15 , further comprising depositing a a semiconductor material on the multi-step surface of the semiconductor region.

17. The method of claim 15 , wherein the semiconductor material includes a group III-V semiconductor material.

18. The method of claim 14 , wherein the etching process includes a Hydrogen Chloride (HCl) etching process.

19. The method of claim 14 , wherein the formation of the multi-step surface is performed in a same chamber as an MOCVD process.

Assignments (1)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jan 31, 2013
From: CHEN, MENG-KU; LIN, HUNG-TA; CHANG, HUICHENG
To: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
Reel/Frame 029736/0222 →
Continuity (1)
Related Publication 20140209974A1 · Jul 31, 2014