Integrated high-k/metal gate in CMOS process flow
A method of fabricating a semiconductor device includes providing a semiconductor substrate having a first active region and a second active region, forming a first metal layer over a high-k dielectric layer, removing at least a portion of the first metal layer in the second active region, forming a second metal layer on first metal layer in the first active region and over the high-k dielectric layer in the second active region, and thereafter, forming a silicon layer over the second metal layer. The method further includes removing the silicon layer from the first gate stack thereby forming a first trench and from the second gate stack thereby forming a second trench, and forming a third metal layer over the second metal layer in the first trench and over the second metal layer in the second trench.
1. A semiconductor device comprising:
a semiconductor substrate that has a first-type active region comprising an NMOS active region adjacent a second-type active region comprising a PMOS active region;
a dielectric layer having a trench disposed directly over the first-type active region and the second-type active region;
a high-k dielectric layer disposed within the trench over the first-type active region and the second-type active region;
a first continuous metal layer having a first work function and disposed over the high-k dielectric layer in the trench, the first metal layer being partially removed from over the second-type active region so that a thickness of the first metal layer overlying the second-type active region is less than a thickness of the first metal layer overlying the first-type active region; and
a second metal layer over the first metal layer in the trench overlying the first-type active region and over the first metal layer in the second-type active region, the second metal layer having a second work function.
2. The semiconductor device of claim 1 in which an NMOS gate stack of the semiconductor device includes the high-k dielectric layer, the first metal layer, and the second metal layer, further in which a PMOS gate stack of the semiconductor device includes the high-k dielectric layer, the first metal layer, and the second metal layer.
3. The semiconductor device of claim 2 in which the NMOS gate stack has a different metal thickness than that of the PMOS gate stack.
4. The semiconductor device of claim 1 in which the first metal in the second-type active region is of a thickness that causes the first metal not to affect the second work function.
5. The semiconductor device of claim 1 further comprising a barrier metal layer and a filler metal layer over the second metal layer.
6. The semiconductor device of claim 1 , wherein a thickness of the high-k dielectric layer is within a range of about 10 to 30 angstroms.
7. The semiconductor device of claim 1 , wherein a thickness of the first metal layer over the first-type active region is within a range of about 10 to 200 angstroms.
8. The semiconductor device of claim 1 , wherein a thickness of the first metal layer over the second-type active region is within a range of about 30-60 angstroms.
9. A semiconductor device comprising:
a semiconductor substrate that has a first-type active region comprising an NMOS active region adjacent a second-type active region comprising a PMOS active region;
a dielectric layer formed on the semiconductor substrate, the dielectric layer comprising a trench disposed over the first-type active region and the second-type active region;
a high-k dielectric layer disposed within the trench over the first-type active region and the second-type active region;
a first, continuous metal layer formed over both the first-type active region and the second-type active region, the first metal layer having a first work function and formed over the high-k dielectric layer, the first metal layer being partially removed from over the second-type active region so that a thickness of the first metal layer overlying the second-type active region is less than a thickness of the first metal layer overlying the first-type active region; and
a second metal layer over the first metal layer in the trench, the second metal layer overlying the first-type active region and over the first metal layer in the second-type active region, the second metal layer having a second work function.
10. The semiconductor device of claim 9 in which an NMOS gate stack of the semiconductor device includes the high-k dielectric layer, the first metal layer, and the second metal layer, further in which a PMOS gate stack of the semiconductor device includes the high-k dielectric layer, the first metal layer, and the second metal layer.
11. The semiconductor device of claim 10 in which the NMOS gate stack has a different metal thickness than that of the PMOS gate stack.
12. The semiconductor device of claim 9 in which the first metal in the second-type active region is of a thickness that causes the first metal not to affect the second work function.
13. The semiconductor device of claim 9 further comprising a barrier metal layer and a filler metal layer over the second metal layer.
14. A semiconductor device comprising:
a semiconductor substrate that has a first-type active region comprising an NMOS active region adjacent a second-type active region comprising a PMOS active region;
a dielectric layer formed on the semiconductor substrate, the dielectric layer comprising a trench disposed over the first-type active region and the second-type active region;
a high-k dielectric layer disposed within the trench over the first-type active region and the second-type active region;
a first, continuous metal layer formed over the first-type active region, the second-type active region, and at least partially along sides of the trench, the first metal layer having a first work function and formed over the high-k dielectric layer, the first metal layer being partially removed from over the second-type active region so that a thickness of the first metal layer overlying the second-type active region is less than a thickness of the first metal layer overlying the first-type active region; and
a second metal layer over the first metal layer in the trench, the second metal layer overlying the first-type active region and over the first metal layer in the second-type active region, the second metal layer having a second work function.
15. The semiconductor device of claim 14 , wherein a thickness of the high-k dielectric layer is within a range of about 10 to 30 angstroms.
16. The semiconductor device of claim 14 , wherein a thickness of the first metal layer over the first-type active region is within a range of about 10 to 200 angstroms.
17. The semiconductor device of claim 14 , wherein a thickness of the first metal layer over the second-type active region is within a range of about 30-60 angstroms.