Reduced signal interface memory device, system, and method
View Patent ↗A memory has a serial interface. The serial interface is programmable to either use separate dedicated input and output pads, or to use one bidirectional pad. When one bidirectional pad is used, the interface signal count is reduced by one.
1. A memory comprising:
a serial data in pad and a serial data out pad;
circuitry configured to configure one of the serial data in pad or the serial data out pad to operate as a bidirectional serial data pad; and
a control unit coupled to the serial data in pad, the control unit configured to receive serial instructions and to configure the circuitry for bidirectional operation.
2. The memory of claim 1 , further comprising a package, wherein only one of the serial data in and serial data out pad is bonded to the package.
3. The memory of claim 1 , further comprising:
a serial shift register coupled to the serial data in pad and the serial data out pad; and
a nonvolatile memory core coupled to the serial shift register.
4. The memory of claim 3 , wherein the nonvolatile memory core comprises FLASH memory.
5. The memory of claim 3 , wherein the nonvolatile memory core comprises phase change memory.
6. The memory of claim 1 , wherein the control unit configured to configure the circuitry for bidirectional operation is responsive to receiving an instruction via the serial data in pad.
7. The memory of claim 6 , wherein the control unit is configured to configure the circuitry for full duplex operation responsive to receiving a second instruction via the serial data in pad.
8. A memory comprising:
circuitry coupled to a serial data in pad and a serial data out pad, the circuitry configured to enable bidirectional communication on one of the serial data in pad or the serial data out pad; and
a control unit coupled to the serial data in pad and configured to control the circuitry to operate in one of a bidirectional mode or a full duplex mode.
9. The memory of claim 8 , wherein the control unit is configured to receive serial instructions from a processor, wherein the control unit configured to control the circuitry to operate in one of the bidirectional mode or the full duplex mode is based on the serial instructions.
10. The memory of claim 8 , wherein the control unit configured to control the circuitry to operate in one of the bidirectional mode or the full duplex mode comprises the control unit configured to provide a control signal to the circuitry.
11. The memory of claim 10 , wherein the circuitry configured to enable bidirectional communication on the one of the serial data in pad or the serial data out pad is responsive to the control signal having a first value.
12. The memory of claim 11 , wherein the circuitry is further configured enable full duplex communication on the serial data in pad and the serial data out pad responsive to the control signal having a second value.
13. The memory of claim 8 , wherein the circuitry configured to enable bidirectional communication on the one of the serial data in pad or the serial data out pad comprises the circuitry coupling the serial data in pad to the serial data out pad.
14. The memory of claim 13 , wherein the circuitry comprises one of a tri-state inverter or a transistor.
15. A method comprising:
enabling bidirectional communication on a first serial port of a memory responsive to a signal from a control unit of the memory having a first value; and
enabling full duplex communication on the first serial port and a second serial port responsive to the signal from the control unit having a second value.
16. The method of claim 15 , further comprising:
setting the signal to the first value responsive to receiving a first instruction; and
setting the signal to the second value responsive to receiving the second instruction.
17. The method of claim 15 , wherein enabling the bidirectional communication on the serial port comprises coupling the first serial port to the second serial port.
18. The method of claim 17 , wherein coupling the first serial port to the second serial port comprises turning on a tri-state buffer.
19. The method of claim 17 , wherein coupling the first serial port to the second serial port comprises closing a transistor switch.
20. The method of claim 17 , the first serial data port comprises a bidirectional data port and the second serial data port comprises a serial data out port.