Methods of forming memory and methods of forming vertically-stacked structures
Some embodiments include constructions having electrically conductive bitlines within a stack of alternating electrically conductive wordline levels and electrically insulative levels. Cavities extend into the electrically conductive wordline levels, and phase change material is within the cavities. Some embodiments include methods of forming memory. An opening is formed through a stack of alternating electrically conductive levels and electrically insulative levels. Cavities are extended into the electrically conductive levels along the opening. Phase change material is formed within the cavities, and incorporated into vertically-stacked memory cells. An electrically conductive interconnect is formed within the opening, and is electrically coupled with a plurality of the vertically-stacked memory cells.
1. A method of forming vertically-stacked structures, comprising:
forming a stack of alternating electrically conductive levels and electrically insulative levels;
forming an electrically insulative panel that extends through the stack;
removing some sections of the panel while leaving other sections remaining; openings being formed where sections of the panel are removed; each opening having a first pair of opposing sides along the stack, and having a second pair of opposing sides along remaining sections of the panel;
forming cavities extending laterally outward from the first pair of opposing sides of each of the openings with the second pair of opposing sides remaining intact, the cavities extending only partially into the electrically conductive levels between electrically insulative levels;
forming first electrode material within the cavities and directly contacting the electrically conductive levels;
forming phase change material within the cavities after forming the first electrode material;
forming second electrode material within the cavities after forming the phase change material;
forming electrically conductive interconnects within the openings and directly contacting the second electrode material; and
forming cell select device material and middle electrode material within the cavities; and wherein the phase change material is spaced from the cell select device material by the middle electrode material.
2. The method of claim 1 wherein the cell select device material is formed prior to the phase change material.
3. The method of claim 1 wherein the cell select device material is formed after the phase change material.
4. The method of claim 1 wherein the electrically insulative panel is formed to comprise a plurality of linear regions joined to one another through curved regions; wherein the linear regions are substantially parallel to one another; and wherein the openings are formed only within the linear regions.
5. The method of claim 4 wherein the electrically conductive levels are wordline levels, wherein the electrically insulative panel divides the wordline levels into a first set and a second set which are separated from one another by the electrically insulative panel; and further comprising electrically connecting all wordlines of the first set at a common elevational level to one another, and electrically connecting all wordlines of the second set at a common elevational level to one another.
6. The method of claim 1 wherein the electrically conductive interconnects comprise metal.
7. A method of forming memory, comprising:
forming a stack of alternating electrically conductive wordline levels and electrically insulative levels;
forming a trench extending through the stack;
forming an electrically insulative panel within the trench;
removing some sections of the panel while leaving other sections remaining; openings being formed where sections of the panel are removed; each opening having a first pair of opposing sides along the stack, and having a second pair of opposing sides along remaining sections of the panel;
forming cavities extending laterally outward from the first pair of opposing sides of each of the openings with the second pair of opposing sides remaining intact, the cavities extending only partially into the electrically conductive wordline levels between electrically insulative levels;
forming first electrode material along exposed edges of the electrically conductive wordline levels within the cavities;
after forming the first electrode material, forming phase change material within cavities;
after forming the phase change material; forming second electrode material within the cavities;
forming electrically conductive bitline material within the openings and spaced from the phase change material by at least the second electrode material; and
forming cell select device material and middle electrode material within the cavities; and wherein the phase change material is spaced from the cell select device material by the middle electrode material.
8. The method of claim 7 wherein the cell select device material is formed prior to the phase change material.
9. The method of claim 7 wherein the cell select device material is formed after the phase change material.
10. The method of claim 7 wherein the trench is formed to comprise a plurality of linear regions joined to one another through curved regions; and wherein the electrically insulative panel formed within the trench comprises a plurality of linear regions joined to one another through curved regions; wherein the linear regions of the panel are substantially parallel to one another; and wherein the openings are formed only within the linear regions of the panel.