Through silicon via metallization

1. A method for filling through silicon vias, comprising:

depositing a dielectric layer over the through silicon vias;

depositing a tungsten containing barrier layer by CVD or ALD over the dielectric layer; and

filling the through silicon vias with a conductive material,

wherein the barrier layer is tungsten nitride and wherein the filling the through silicon vias, comprises:

using electroless deposition to deposit a nickel or nickel alloy seed layer over the tungsten nitride barrier layer; and

using electroplating to fill the through silicon vias with a copper or copper alloy.

2. The method, as recited in claim 1 , further comprising CVD, ELD, ECP or ALD of nickel, cobalt, palladium, or alloys, containing one or more of these elements, forming an intermediate adhesion transition over the barrier layer.

3. The method, as recited in claim 2 , wherein the dielectric layer is a silicon oxide based material.

4. The method, as recited in claim 1 , further comprising planarizing parts of the conductive material, barrier layer, and a seed layer.

5. The method, as recited in claim 1 , wherein the filling the through silicon vias further comprises:

using electroplating to deposit a seed layer over the nickel or nickel alloy layer.

6. The method, as recited in claim 1 , wherein the filling the through silicon vias further comprises:

using CVD or ALD to deposit a tungsten or other tungsten containing layer such as tungsten silicide or tungsten titanium layer over the tungsten nitride barrier layer.

7. The method, as recited in claim 1 , wherein the barrier layer is tungsten nitride and wherein the filling the through silicon vias, comprises:

using CVD or ALD to deposit a tungsten layer over the tungsten nitride barrier layer; and

using electroplating to deposit a seed layer over the ELD layer.

8. The method, as recited in claim 1 , wherein the through silicon vias have a depth of at least 20 μm.

9. The method, as recited in claim 1 , wherein the dielectric layer is a silicon oxide based material.

10. The method, as recited in claim 1 , further comprising planarizing parts of the conductive material, barrier layer, and a seed layer.

11. The method, as recited in claim 1 , further comprising CVD, ELD, ECP or ALD of nickel or nickel alloy of these forming an intermediate adhesion transition over the barrier layer.

12. The method, as recited in claim 1 , further comprising: CVD, ELD, ECP or ALD of nickel, cobalt, palladium, or alloys containing one or more of these elements forming an intermediate adhesion transition over the barrier layer, wherein the filling the through silicon vias uses an electrolytic copper plating process.

13. The method, as recited in claim 1 , further comprising:

forming a first intermediate adhesion transition layer of Ni, Co, or Pd, or alloys, containing one or more of these elements by CVD, ELD or ALD over the barrier layer; and

forming a second intermediate adhesion transition layer of Cu or Cu alloys by CVD, ELD, or ALD over the first intermediate adhesion transition layer.

14. A semiconductor structure with conductive fillings in through silicon vias formed by a method, comprising:

depositing a dielectric layer over the through silicon vias;

depositing a tungsten containing barrier layer by CVD or ALD over the dielectric layer; and

filling the through silicon vias with a conductive material,

wherein the method further comprises CVD, ELD, ECP or ALD of nickel or nickel alloy over the barrier layer.

15. The semiconductor structure, as recited in claim 14 , further comprising CVD, ELD, ECP or ALD of nickel, cobalt, palladium or combination or alloy of these forming an intermediate adhesion transition over the barrier layer.

16. The semiconductor structure, as recited in claim 15 , wherein the filling the through silicon vias uses an electrolytic copper plating process.

17. The semiconductor structure, as recited in claim 14 , wherein the filling the through silicon vias uses an electroless deposition process.

18. The semiconductor structure, as recited in claim 17 , wherein the barrier layer is tungsten nitride.

19. The semiconductor structure, as recited in claim 18 , wherein the dielectric layer is a silicon oxide based material.

20. The semiconductor structure, as recited in claim 19 , wherein the conductive material is a copper or copper alloy.

21. The semiconductor structure, as recited in claim 20 , wherein the method further comprises planarizing parts of the conductive material, barrier layer, and a seed layer.

22. The semiconductor structure, as recited in claim 14 , wherein the filling the through silicon vias, comprises using electroplating to fill the through silicon vias with a copper or copper alloy.

23. The semiconductor structure, as recited in claim 14 , wherein the filling the through silicon vias uses an electroless deposition process.

24. The semiconductor structure, as recited in claim 14 , wherein the barrier layer is tungsten nitride.

25. The semiconductor structure, as recited in claim 14 , wherein the conductive material is a copper or copper alloy.

26. The semiconductor structure, as recited in claim 14 , wherein the wherein the through silicon vias have a depth of at least 20 μm.

27. The semiconductor structure, as recited in claim 14 , wherein the dielectric layer is a silicon oxide based material.

28. The semiconductor structure, as recited in claim 14 , wherein the method further comprises planarizing parts of the conductive material, barrier layer, and a seed layer.

29. A semiconductor structure, comprising:

a silicon substrate with through silicon vias features etched into the silicon substrate;

a dielectric layer over the through silicon via features;

a barrier layer comprising tungsten over the dielectric layer;

a conductive filling within the via features; and

a nickel or nickel alloy layer between the barrier layer and the conductive filling.

30. The semiconductor structure, as recited in claim 29 , wherein the barrier layer is tungsten nitride.

31. The semiconductor structure, as recited in claim 30 , wherein the dielectric layer is silicon oxide based.

32. The semiconductor structure, as recited in claim 31 , wherein the conductive filling is copper or copper alloy.

33. The semiconductor structure, as recited in claim 32 , wherein the wherein the through silicon vias have a depth of at least 20 μm.

34. The semiconductor structure, as recited in claim 29 , further comprising an intermediate adhesion transition layer comprising nickel, cobalt, palladium, or a combination or alloy thereof between the barrier layer and the conductive filling.