Circuit and system for testing a one-time programmable (OTP) memory
View Patent ↗Circuits, systems and techniques for testing a One-Time Programmable (OTP) memory are disclosed. An extra OTP bit can be provided as a test sample to be programmed. The programmed extra OTP bit can be read with any virgin cells in the OTP memory alternatively to generate a stream of logic 0 and logic 1 data so that every row or column path can be tested and the outcome can be observed in a pseudo-checkerboard pattern or other predetermined pattern. By carefully setting control signals, checkerboard-like pattern can be generated without actual programming any OTP cells in the memory array.
1. A One-Time Programmable (OTP) memory, comprising:
a plurality of OTP cells, at least one of the OTP cells comprising:
a program selector with an enable signal coupled to a wordline (WL);
an OTP element with one end coupled to the program selector and another end coupled to a bitline (BL); and
the OTP cells being organized as a two-dimensional array with the WLs of the OTP cells in the same rows coupled to a WL and the BLs of the OTP cells in the same columns coupled to a BL;
at least one sense amplifier coupled to at least one BLs to generate a logic state;
at least one row or column decoders to select one row or one column from the OTP memory; and
at least one control signal coupled to the row or column decoders to turn on or off any adjacent rows or columns,
wherein test patterns are be generated with alternative logic 0 and 1 states by setting a combination of the control signals to turn on at least one row or columns through at least one sense amplifiers to read from at least one OTP cells.
2. An OTP memory as recited in claim 1 , wherein the control signals are coupled to at least one address buffers are coupled to a row or column decoder.
3. An OTP memory as recited in claim 1 , wherein the sense amplifier has a plurality of reference resistors for selection.
4. An OTP memory as recited in claim 1 , wherein the sense amplifier has a test device that has a control signal to sweep the device into different resistance values, wherein the equivalent resistance of the device is used as a test reference resistance to sense the OTP cells.
5. A sense amplifier as recited in claim 4 , wherein the test device can be monitored for voltage or current during sweep tests.
6. An OTP memory as recited in claim 1 , wherein the OTP element is a fuse that includes at least one of polysilicon, silicided polysilicon, silicide, polymetal, metal, metal alloy, thermally isolated active region, CMOS gate, contact, or via.
7. An OTP memory as recited in claim 1 , wherein the OTP element is an anti-fuse that includes at least one of contact/via with dielectric in between gate and MOS body with gate oxide in between.
8. An OTP memory as recited in claim 1 , wherein at least one of the OTP cells has at least one program selector that is a junction diode constructed from an isolated active region on a CMOS well, and wherein the two terminals of the junction diode are implanted with the same source or drain implant in a CMOS process.
9. An OTP memory as recited in claim 1 , wherein at least one of the OTP cells have at least one program selector that is a polysilicon or isolated active-region diode built on a polysilicon or isolated active-region structure, and wherein the two terminals of the diode are implanted with the same source or drain implant in a CMOS process.
10. An electronics system, comprising:
a processor; and
an OTP memory operatively connected to the processor, the OTP memory includes at least a plurality of OTP cells for providing data storage, each of the OTP cells comprising:
a program selector with an enable signal coupled to a wordline (WL);
an OTP element with one end coupled to the program selector and another end coupled to a bitline (BL); and
the OTP cells being organized as a two-dimensional array with the WLs of the OTP cells in the same rows coupled to a WL and the BLs of the OTP cells in the same columns coupled to a BL;
at least one sense amplifier coupled to at least one BLs to generate a logic state;
at least one row or column decoders to select one row or one column from the OTP memory; and
at least one control signal coupled to at least one row or column decoders to turn on or off any adjacent rows or columns,
wherein test patterns are be generated with alternative logic 0 and 1 states by setting a combination of the control signals to turn on at least one row or columns through at least one sense amplifiers to read from at least one OTP cells.
11. An OTP memory as recited in claim 10 , wherein the control signals are coupled to at least one address buffer coupled to a row or column decoder.
12. An OTP memory as recited in claim 10 , wherein the sense amplifier has a plurality of reference resistors for selection.
13. An OTP memory as recited in claim 10 , wherein the sense amplifier has a test device that has a control signal to sweep the device into different resistance values, wherein the equivalent resistance of the device is used as a test reference resistance to sense the OTP cells.
14. An OTP memory as recited in claim 13 , wherein the test device can be monitored for voltage or current during sweep tests.
15. An OTP memory as recited in claim 10 , wherein the OTP element is a fuse that includes at least one of polysilicon, silicided polysilicon, silicide, polymetal, metal, metal alloy, thermally isolated active region, CMOS gate, contact, or via.
16. An OTP memory as recited in claim 10 , wherein the OTP element is an anti-fuse that includes at least one of contact/via with dielectric in between gate and MOS body with gate oxide in between.
17. An OTP memory as recited in claim 10 , wherein at least one of the OTP cells has at least one program selector that is a junction diode constructed from an isolated active region on a CMOS well, and wherein the two terminals of the junction diode are implanted with the same source or drain implant in a CMOS process.
18. An OTP memory as recited in claim 10 , wherein at least one of the OTP cells has at least one program selector that is a polysilicon or isolated active-region diode built on a polysilicon or isolated active-region structure, and wherein the two terminals of the diode are implanted with the same source or drain implant in a CMOS process.
19. A method for testing a One-Time Programmable (OTP) memory, comprising:
providing a plurality of OTP cells, at least one of the OTP cells include at least one OTP element coupled to a bitline (BL) and to at least one program selector with an enable signal, at least one of the OTP cells being organized as a two-dimensional array with the BLs of the OTP cells in the same columns coupled as single BL and the enable signal of the OTP cells in the same rows coupled as a single WL, at least one row or column decoder to generate signals to select at least one row or column, at least one sense amplifier coupled to at least one BLs to sense at least one OTP cell into logic states, and at least one control signal coupled to at least one row or column decoders to turn on or off any two adjacent rows or columns; and
generating test patterns with alternative logic 0 and 1 states by setting the control signals to turn on or off the selected rows or columns through the at least one sense amplifier.