Logic signal transmission circuit with isolation barrier
A logic signal transmission circuit includes a driving circuit, an isolation section, and a latch section. The driving circuit converts an input digital signal to a differential digital signal. The isolation section blocks direct current and passes the differential digital signal. The latch section has even numbers of inverters which are connected in a loop and output a logic signal by turning ON and OFF a power supply voltage in a complementary manner. An input impedance of the latch section is set so that when a logic level of the differential digital signal changes, a transient voltage inputted through the isolation section to the latch section changes across a threshold voltage of the latch section. When the transient voltage changes across the threshold voltage, a logic level of the logic signal changes.
1. A logic signal transmission circuit comprising:
a driving circuit configured to convert an input digital signal to a differential signal pair having a first digital signal and a second digital signal;
an isolation section configured to block direct current and to pass the differential signal pair, the isolation section including a first isolation barrier and a second isolation barrier, the first isolation barrier configured to pass the first digital signal, the second isolation barrier configured to pass the second digital signal; and
a latch section including a first latch circuit connected to an output terminal of the first isolation barrier and a second latch circuit connected to an output terminal of the second isolation barrier, wherein
the first latch circuit has even numbers of first inverters which are connected in a first loop and configured to output a first logic signal by turning ON and OFF a power supply voltage in a complementary manner,
a first input impedance of the first latch circuit is set so that when a logic level of the first digital signal changes, a first transient voltage inputted through the first isolation barrier to the first latch circuit changes across a first threshold voltage of the first latch circuit,
when the first transient voltage changes across the first threshold voltage, a logic level of the first logic signal changes,
the second latch circuit has even numbers of second inverters which are connected in a second loop and configured to output a second logic signal by turning ON and OFF a power supply voltage in a complementary manner,
a second input impedance of the second latch circuit is set so that when a logic level of the second digital signal changes, a second transient voltage inputted through the second isolation barrier to the second latch circuit changes across a second threshold of the second latch circuit, and
when the second transient voltage changes across the second threshold voltage, a logic level of the second logic signal changes.
2. The logic signal transmission circuit according to claim 1 , wherein
the first input impedance of the first latch circuit is formed by connecting a first resistor to the first inverters, and
the second input impedance of the second latch circuit is formed by connecting a second resistor to the second inverters.
3. The logic signal transmission circuit according to claim 1 , wherein
the first inverters of the first latch circuit are constructed with first transistors,
the first input impedance of the first latch circuit is formed by an internal resistance of at least one of the first transistors,
the second inverters of the second latch circuit are constructed with second transistors, and
the second input impedance of the second latch circuit is formed by an internal resistance of at least one of the second transistors.
4. The logic signal transmission circuit according to claim 1 , wherein
an output terminal of an odd numbered inverter of the first inverters of the first latch circuit is connected to an output terminal of an even numbered inverter of the second inverters of the second latch circuit to form an input terminal of the first latch circuit, and
an output terminal of an even numbered inverter of the first inverters of the first latch circuit is connected to an output terminal of an odd numbered inverter of the second inverters of the second latch circuit to form an input terminal of the second latch circuit.
5. The logic signal transmission circuit according to claim 1 , further comprising:
a first circuit including a first NOT gate, a second NOT gate, a first NOR gate, and a second NOR gate; and
a second circuit including a RS flip-flop connected to an output terminal of the first circuit to hold an output of the first circuit, wherein
a series circuit of the first NOT gate and the first NOR gate is connected to an output terminal of the first latch circuit,
the output terminal of the first latch circuit is connected to an input terminal of the second NOR gate,
a series circuit of the second NOT gate and the second NOR gate is connected to an output terminal of the second latch circuit, and
the output terminal of the second latch circuit is connected to an input terminal of the first NOR gate.
6. The logic signal transmission circuit according to claim 1 , further comprising:
an output holding circuit configured to hold an output of the latch section.
7. The logic signal transmission circuit according to claim 1 , wherein
each of the first inverters of the first latch circuit and the second inverters of the second latch circuit is a Schmitt trigger inverter.
8. The logic signal transmission circuit according to claim 1 , wherein
the isolation section includes a transformer configured to pass the differential signal pair.
9. The logic signal transmission circuit according claim 1 , wherein
the isolation section includes a capacitor, and
the capacitor has a first electrical conductor, a second electrical conductor, and an electrical insulator sandwiched between the first electrical conductor and the second electrical conductor.
10. The logic signal transmission circuit according to claim 9 , wherein
the second electrical conductor has a bonding pad,
an output terminal of the driving circuit is electrically connected to the first electrical conductor, and
an input terminal of the latch section is connected to the bonding pad through a bonding wire.
11. The logic signal transmission circuit according to claim 10 , wherein
the driving circuit and the capacitor are implemented on a first semiconductor chip,
the latch section is implemented on a second semiconductor chip different from the first semiconductor chip, and
the first semiconductor chip and the semiconductor chip are packaged in a common package and connected together through the bonding wire inside the package.
12. The logic signal transmission circuit according to claim 9 , wherein
the second electrical conductor has a bonding pad,
an output terminal of the driving circuit is connected to the bonding pad through a bonding wire, and
an input terminal of the latch section is electrically connected to the first electrical conductor.
13. The logic signal transmission circuit according to claim 12 , wherein
the driving circuit is implemented on a first semiconductor chip,
the capacitor and the latch section are implemented on a second semiconductor chip different from the first semiconductor chip, and
the first semiconductor chip and the semiconductor chip are packaged in a common package and connected together through the bonding wire inside the package.
14. The logic signal transmission circuit according to claim 9 , wherein
each of the first input impedance and the second input impedance of the latch section is adjusted according to a capacitance of the capacitor.
15. The logic signal transmission circuit according to claim 9 , wherein
each of the first electrical conductor and the second electrical conductor is made of metal or silicon.