DRAM WITH SEGMENTED PAGE CONFIGURATION
This description is directed to a dynamic random access memory (DRAM) array having a plurality of rows and a plurality of columns. The array further includes a plurality of cells, each of which are associated with one of the columns and one of the rows. Each cell includes a capacitor that is selectively coupled to a bit line of its associate column so as to share charge with the bit line when the cell is selected. There is a segmented word line circuit for each row, which is controllable to cause selection of only a portion of the cells in the row.
1 . A dynamic random access memory (DRAM) array, comprising:
a plurality of rows;
a plurality of columns;
a plurality of cells, each being associated with one of the columns and with one of the rows, where each cell includes a capacitor that is selectively coupled to a bit line of its associated column so as to share charge with the bit line when the cell is selected; and
a segmented word line circuit for each row, the segmented word line circuit being controllable to cause selection of only a portion of the cells in that row.
2 . The DRAM array of claim L where for each row, the segmented word line circuit includes:
a global word line; and
a plurality of local word lines that are each coupled with the global word line and an associated subpage of the cells in the row, where the cells of a given subpage are selected to share charge with their bit lines by (i) asserting the global word line and (ii) gating the asserted global word line with an asserted subpage select signal in order to assert the local word line coupled with the given subpage of cells.
3 . The DRAM array of claim 1 , further comprising a decoder configured to generate subpage select signals that control which bit lines of the DRAM array are involved in a commanded DRAM operation.
4 . The DRAM array of claim 3 , where the commanded DRAM operation is a command to have cells in a row share the charge of their capacitors with the bit lines of their associated columns, the subpage select signals therefore controlling which bit lines are involved in such charge sharing.
5 . The DRAM array of claim 3 , where the commanded DRAM operation is a command to precharge bit lines, the subpage select signals therefore controlling which bit lines are precharged.
6 . The DRAM array of claim 3 , further comprising, for each column, a sense amp coupled to a bit line of the column, and where the commanded DRAM operation is a command to enable the sense amps to sense charge levels on their coupled bit lines, the subpage select signals therefore controlling which sense amps perform such charge sensing.
7 . The DRAM array of claim 6 , where the sense amps are configured to generate an output indicative of whether a cell that has shared charge with the bit line was storing a logical HI or logical LO voltage level.
8 . The DRAM array of claim 7 , further comprising a latch coupled to each of the sense amps and operative to store the output of the sense amp.
9 . A dynamic random access memory (DRAM) array, comprising:
a plurality of rows;
a plurality of columns;
a plurality of cells, each being associated with one of the columns and with one of the rows; and
a decoder configured to generate subpage select signals that control which columns of the DRAM array are involved in a commanded DRAM operation.
10 . The DRAM array of claim 9 , were each cell includes a capacitor that is selectively coupled to a bit line of its associated column so as to share charge with the bit line when the cell is selected, and where the commanded DRAM operation is a command that selected capacitors in a selected row share charge with their associated bit lines, the specific capacitor selection being caused by the subpage select signals.
11 . The DRAM array of claim 9 , where each column includes a pair of bit lines coupled with a sense amp, and where the commanded DRAM operation is command to precharge selected bit lines, the specific bit line selection being caused by the subpage select signals.
12 . The DRAM array of claim 9 , where each column includes a pair of bit lines coupled with a sense amp, and where the commanded DRAM operation is a command to enable selected sense amps to sense charge levels on their coupled bit lines, the specific sense amp selection being caused by the subpage select signals.
13 . The DRAM array of claim 9 , where the decoder is controllable to provide variable page width operation such that, for a given one of the rows, the decoder is operable to activate a portion of the row which varies in size based on an output of the decoder.
14 . A dynamic random access memory (DRAM) array, comprising:
a plurality of rows;
a plurality of columns;
a plurality of cells, each being associated with one of the columns and with one of the rows, where each cell includes a capacitor that is selectively coupled to a bit line of its associated column so as to share charge with the bit line when the cell is selected; and
a segmented word line circuit for each row where the segmented word line circuit includes a global word line and a plurality of local word lines that are each coupled with the global word line and an associated subpage of the cells in the row, where the cells of a given subpage are selected to share charge with their bit lines by (i) asserting the global word line and (ii) gating the asserted global word line with an asserted subpage select signal in order to assert the local word line coupled with the given subpage of cells.
15 . The DRAM array of claim 14 , further comprising a decoder configured to generate the subpage select signal.
16 . The DRAM array of claim 15 , where the decoder is further configured to generate signals to select rows and columns for use in DRAM operations.
17 . The DRAM array of claim 14 , further comprising a plurality of subpage select lines.
18 . The DRAM array of claim 17 , where each of the subpage select lines is associated with a subset of the plurality of columns.
19 . The DRAM array of claim 18 , where for each subset of the plurality of columns, each row has a local word line for the subpage of cells in those columns, the associated subpage select line being configured to select the local word line of the subset of the plurality of columns.
20 . The DRAM array of claim 18 , where for each subset of the plurality of columns, each column within the subset has a sense amp that is selectively enabled by the subpage select line associated with the subset of the plurality of columns.
21 . The DRAM array of claim 20 , where for each subset of the plurality of columns, each column has a latch coupled to its sense amp, the latch being triggered by the subpage select line associated with the subset of the plurality of columns.