Memory controller, semiconductor memory system, and memory control method

1. A memory system comprising:

a non-volatile semiconductor memory that includes memory cells each storing 3 bits, and each bit data of the 3 bits data is allocated to each threshold value distribution;

a control unit that performs control such that the threshold value distribution is allocated by first data coding in which a first page, a second page, and a third page are each 1 bit and data is written to the non-volatile semiconductor memory, a first bit of the 3 bits data indicating data of the first page, a second bit thereof indicating data of the second page, and a third bit thereof indicating data of the third page; and

an encoding unit that generates a first parity with a first size for user data stored in the first page, generates a second parity with a second size for user data stored in the second page, and generates a third parity with a third size for user data stored in the third page,

wherein the control unit performs control such that the user data, the first parity, the third parity, and a portion of the second parity are written to the non-volatile semiconductor memory by the first data coding and performs control such that a portion of the second parity and a portion of the third parity are allocated to each threshold value by second data coding in which the first page is 0 bit, the second page is 2 bits, and the third page is 1 bit and are written to the non-volatile semiconductor memory.

2. The memory system according to claim 1 ,

wherein in the second page, there are three boundaries in the first data coding.

3. The memory system according to claim 1 ,

wherein the control unit performs control such that a portion of the first parity is written to the non-volatile semiconductor memory by the first data coding and performs control such that a portion of the third parity and a portion of the first parity are written to the non-volatile semiconductor memory by third data coding in which the third page is 0 bit, the second page is 2 bits, and the first page is 1 bit.

4. The memory system according to claim 1 , further comprising:

an error correction processing unit that corrects an error in the user data of the first page using the first parity read from the non-volatile semiconductor memory, corrects an error in the user data of the second page using the second parity written by the first data coding and the second parity written by the second data coding which are read from the non-volatile semiconductor memory, and corrects an error in the user data of the third page using the third parity written by the first data coding and the third parity written by the second data coding which are read from the non-volatile semiconductor memory.

5. The memory system according to claim 1 ,

wherein the encoding unit generates at least one of the first parity and the third parity using a multi-stage error correction method in which a generation polynomial used to generate a parity in an i-th stage (i is an integer equal to or greater than 1 and equal to or less than n) is selected on the basis of a generation polynomial used to generate parities in first to (i−1)-th stages.

6. The memory system according to claim 5 , further comprising:

an error correction processing unit that corrects an error in the user data of the second page using the second parity written by the first data coding, the second parity written by the second data coding, and the second parity written by the third data coding, corrects an error in the user data of the first page using the parity in the first stage in the first parity, corrects an error in the user data of the first page using the parities in the first and second stages in the first parity and an error in the user data of the third page using the parity in the first stage in the third parity when the correction of the error by the error correction is not available, and corrects an error in the user data of the third page using the parities in the first and second stages in the third parity when the correction of the error by the error correction is not available.

7. The memory system according to claim 5 ,

wherein the encoding unit sets the number of stages in the multi-stage error correction method to 2, further generates the parity in the second stage in the first parity as a first external parity, and further generates the parity in the second stage in the third parity as a second external parity, and

the control unit performs control such that the parity in the first stage in the first parity and the parity in the first stage in the third parity are written to the non-volatile semiconductor memory by the first data coding, performs control such that the parity in the second stage in the first parity and a portion of the second parity are written to the non-volatile semiconductor memory by the second data coding, performs control such that the parity in the second stage in the third parity and a portion of the second parity are written to the non-volatile semiconductor memory by third data coding in which the third page is 0 bit, the second page is 2 bits, and the first page is 1 bit, and performs control such that the first external parity and the second external parity are written to the non-volatile semiconductor memory by the data coding.

8. The memory system according to claim 5 ,

wherein the number of stages in the multi-stage error correction method is 2,

the control unit performs control such that the parity in the first stage in the first parity and the parity in the first stage in the third parity are written to the non-volatile semiconductor memory by the first data coding, performs control such that the parity in the second stage in the first parity and a portion of the second parity are written to the non-volatile semiconductor memory by the second data coding, and performs control such that the parity in the second stage in the third parity and a portion of the second parity are written to the non-volatile semiconductor memory by third data coding in which the third page is 0 bit, the second page is 2 bits, and the first page is 1 bit.

9. The memory system according to claim 1 ,

wherein the encoding unit generates the first parity and the third parity using a multi-grain multi-stage error correction method in which a generation polynomial used to generate a parity in an i-th stage (i is an integer equal to or greater than 1 and equal to or less than n) is selected on the basis of a generation polynomial used to generate parities in first to (i−1)-th stages and a user data size varies depending on the stage.

10. The memory system according to claim 9 ,

wherein the encoding unit generates the parity in the first stage in the first parity using the user data of the first page, generates the parity in the first stage in the third parity using the user data of the third page, and generates the parity in the second stage, which is common to the first page and the third page, using the parity in the first stage in the first parity, the user data of the first page, the parity in the first stage in the third parity, and the user data of the third page, and

the control unit performs control such that the parity in the first stage in the first parity and the parity in the first stage in the third parity are written to the non-volatile semiconductor memory by the first data coding, performs control such that a portion of the common parity and a portion of the second parity are written to the non-volatile semiconductor memory by the second data coding, and performs control such that a portion of the common parity and a portion of the second parity are written to the non-volatile semiconductor memory by third data coding in which the third page is 0 bit, the second page is 2 bits, and the first page is 1 bit.

11. The memory system according to claim 9 ,

wherein the encoding unit generates the parity in the first stage in the first parity using the user data of the first page, generates the parity in the first stage in the third parity using the user data of the third page, generates the parity in the second stage, which is common to the first page and the third page, using the parity in the first stage in the first parity, the user data of the first page, the parity in the first stage in the third parity, and the user data of the third page, and generates the common parity as an external parity, and

the control unit performs control such that the parity in the first stage in the first parity, the parity in the first stage in the third parity, and the external parity are written to the non-volatile semiconductor memory by the first data coding, performs control such that a portion of the common parity and a portion of the second parity are written to the non-volatile semiconductor memory by the second data coding, and performs control such that a portion of the common parity and a portion of the second parity are written to the non-volatile semiconductor memory by third data coding in which the third page is 0 bit, the second page is 2 bits, and the first page is 1 bit.

12. A memory controller that controls a non-volatile semiconductor memory which includes memory cells each storing 3 bits, and each bit data of the 3 bits data is allocated to each threshold value distribution, comprising:

a control unit that performs control such that the threshold value distribution is allocated by first data coding in which a first page, a second page, and a third page are each 1 bit and data is written to the non-volatile semiconductor memory, a first bit of the 3 bits data indicating data of the first page, a second bit thereof indicating data of the second page, and a third bit thereof indicating data of the third page; and

an encoding unit that generates a first parity with a first size for user data stored in the first page, generates a second parity with a second size for user data stored in the second page, and generates a third parity with a third size for user data stored in the third page,

wherein the control unit performs control such that the user data, the first parity, the third parity, and a portion of the second parity are written to the non-volatile semiconductor memory by the first data coding and performs control such that a portion of the second parity and a portion of the third parity are allocated to each threshold value by second data coding in which the first page is 0 bit, the second page is 2 bits, and the third page is 1 bit and are written to the non-volatile semiconductor memory.

13. A memory control method that controls a non-volatile semiconductor memory which includes memory cells each storing 3 bits, and each bit data of the 3 bits data is allocated to each threshold value distribution, comprising:

performing control such that the threshold value distribution is allocated by first data coding in which a first page, a second page, and a third page are each 1 bit and data is written to the non-volatile semiconductor memory, a first bit of the 3 bits data indicating data of the first page, a second bit thereof indicating data of the second page, and a third bit thereof indicating data of the third page;

generating a first parity with a first size for user data stored in the first page, generating a second parity with a second size for user data stored in the second page, and generating a third parity with a third size for user data stored in the third page; and

performing control such that the user data, the first parity, the third parity, and a portion of the second parity are written to the non-volatile semiconductor memory by the first data coding and performing control such that a portion of the second parity and a portion of the third parity are allocated to each threshold value by second data coding in which the first page is 0 bit, the second page is 2 bits, and the third page is 1 bit and are written to the non-volatile semiconductor memory.