Double channel doping in transistor formation
View Patent ↗A method includes performing a first well doping on a first active region and a second active region simultaneously, and forming a first and a second dummy gate covering a first middle portion of the first active region and a second middle portion of the second active region, respectively. The first and the second dummy gates are removed, and the second middle portion of the second active region is covered with a mask. A second well doping is performed on the first middle portion when the mask is on the second middle portion. After the second well doping, a first gate dielectric and a first gate electrode are formed on the first middle portion to form a first transistor, and a second gate dielectric and a second gate electrode are formed on the second middle portion to form a second transistor.
1. A method comprising:
performing a first well doping on a first active region and a second active region simultaneously;
forming a first dummy gate covering a first middle portion of the first active region;
forming a second dummy gate covering a second middle portion of the second active region;
removing the first and the second dummy gates;
after the step of removing the first and the second dummy gates, masking the second middle portion of the second active region with a mask;
performing a second well doping on the first middle portion when the mask is on the second middle portion, wherein end portions of the first active region on opposite sides of the first middle portion are masked during the second well doping;
after the second well doping, forming a first gate dielectric and a first gate electrode on the first middle portion to form a first transistor; and
forming a second gate dielectric and a second gate electrode on the second middle portion to form a second transistor.
2. The method of claim 1 , wherein each of the first active region and the second active region is between isolation regions, and wherein the method further comprises:
recessing the isolation regions, wherein top portions of the first active region and the second active region over top surfaces of remaining portions of the isolation regions form semiconductor fins, and wherein the first and the second dummy gates are formed on sidewalls and top surfaces of the semiconductor fins, respectively.
3. The method of claim 2 further comprising, after the semiconductor fins are formed, performing an implantation to form anti-punch-through regions in the first and the second active regions.
4. The method of claim 1 further comprising forming a Static Random Access Memory (SRAM) cell, wherein the first transistor is comprised in the SRAM cell.
5. The method of claim 1 , wherein in the first well doping and the second well doping, impurities with a same conductivity type are introduced.
6. The method of claim 1 , wherein during the step of performing the second well doping, an entirety of the second active region is masked from receiving the second well doping.
7. The method of claim 1 , wherein the second well doping is performed by implanting through a dummy gate dielectric, and wherein the dummy gate dielectric is disposed over the first middle portion of the first active region.
8. A method of forming a transistor in a Static Random Access Memory (SRAM) cell, the method comprising:
performing a first well doping on an active region;
after the first well doping, forming a dummy gate covering a middle portion of the active region, wherein end portions of the active region on opposite sides of the middle portion of the active region are exposed;
forming an Inter-Layer Dielectric (ILD) over the active region, wherein the ILD overlaps the end portions;
removing the dummy gate to form a recess in the ILD;
performing a second well doping through the recess, wherein the middle portion of the active region is doped during the second well doping; and
forming a gate dielectric and a gate electrode in the recess to form the transistor, wherein the middle portion forms a channel region of the transistor.
9. The method of claim 8 , wherein the transistor is a Fin Field-Effect Transistor (FinFET), and wherein the active region comprises a semiconductor fin.
10. The method of claim 9 further comprising recessing isolation regions on opposite sides of the semiconductor fin.
11. The method of claim 10 further comprising, after the step of recessing the isolation regions, forming anti-punch-through regions in a semiconductor region underlying the semiconductor fin, wherein in the step of forming the anti-punch-through regions and the first well doping, impurities of a same conductivity type are implanted.
12. The method of claim 8 , wherein in the first well doping and the second well doping, impurities of a same conductivity type are implanted.
13. The method of claim 8 , wherein the second well doping has a dosage between about 3E12/cm 2 and about 3E14/cm 2 .
14. The method of claim 8 , wherein during a period starting from the first well doping is performed and ending at a time after source and drain contact plugs of the transistor is formed, no pocket region is formed for the transistor.
15. A method comprising:
performing a first well implantation on a first and a second semiconductor strip simultaneously, wherein the first and the second semiconductor strips are between isolation regions;
recessing the isolation regions, wherein top portions of the first and the second semiconductor strips form a first and a second semiconductor fin, respectively;
forming a first and a second dummy gate covering a first middle portion and a second middle portion of the first and the second semiconductor fins, respectively;
forming an Inter-Layer Dielectric (ILD), wherein the ILD overlaps end portions of the first and the second semiconductor fins;
removing the first and the second dummy gates to form a first recess and a second recess, respectively, in the ILD;
forming a mask, wherein the mask covers the second middle portion of the second semiconductor fin, and wherein the first middle portion of the first semiconductor fin under an opening in the mask;
performing a second well implantation on the first middle portion, wherein impurities of a same conductivity type are introduced by the first well doping and the second well doping; and
after the second well implantation, removing the mask.
16. The method of claim 15 further comprising, after the mask is removed:
forming a first gate dielectric and a first gate electrode on the first middle portion and in the first recess to form a first FinFET; and
forming a second gate dielectric and a second gate electrode on the second middle portion and in the second recess to form a second FinFET.
17. The method of claim 15 further comprising forming a Static Random Access Memory (SRAM) cell, wherein the first semiconductor fin is a part of a transistor in the SRAM cell.
18. The method of claim 15 further comprising:
forming a dummy gate dielectric over the first middle portion, wherein the second well implantation is performed through the dummy gate dielectric, and wherein the method comprises, after the second well implantation, removing the dummy gate dielectric.
19. The method of claim 15 , wherein the first well implantation has a dosage between about 1E12/cm 2 and about 5E14/cm 2 , and wherein the second well implantation has a dosage between about 3E12/cm 2 and about 3E14/cm 2 .
20. The method of claim 15 further comprising, after the step of recessing the isolation regions, performing an anti-punch-through implantation to form anti-punch-through regions underlying the first and the second semiconductor fins.