Memory subsystem I/O performance based on in-system empirical testing

1. A method comprising:

receiving a host memory subsystem on a host hardware platform, the host memory subsystem including a memory device;

establishing respective settings for each of multiple different I/O (input/output) circuit parameters for a target I/O performance characteristic for communication with the memory device by performing the following:

setting a respective value for each I/O circuit parameter;

generating test traffic with a test engine embedded in the host memory subsystem to stress test the memory device; and

measuring an operating margin for the I/O performance characteristic;

repeating the setting, generating and measuring for different values of at least one of the I/O circuit parameters so that a plurality of measurements for different I/O circuit parameter settings is made;

executing a search function to determine values for each I/O circuit parameter at which the operating margin meets a minimum threshold, wherein the search function extrapolates from the plurality of measurements to a worst case condition; and

setting runtime values for the I/O circuit parameters based on the execution of the search function.

2. The method of claim 1 , wherein the memory device comprises a DRAM (dynamic random access memory) device.

3. The method of claim 1 , wherein the target I/O performance characteristic comprises:

power consumption of the memory subsystem.

4. The method of claim 1 , wherein the target I/O performance characteristic comprises:

operating frequency of the memory subsystem.

5. The method of claim 1 , wherein the target I/O performance characteristic comprises:

I/O latency of the memory subsystem.

6. The method of claim 1 , wherein setting the value for the I/O circuit parameter comprises:

setting one of an output resistance of a transmitter, or an input resistance of a receiver.

7. The method of claim 1 , wherein setting the value for the I/O circuit parameter comprises:

setting a slew rate of an output driver or a value of an equalization stage.

8. The method of claim 1 , wherein setting the value of the I/O circuit parameter comprises:

setting a value of a turnaround time.

9. The method of claim 1 , wherein setting the value of the I/O circuit parameter comprises:

setting parameters of a receive circuit separately from a transmit circuit.

10. The method of claim 1 , wherein setting the value of the I/O circuit parameter comprises:

adjusting an operating voltage or a temperature.

11. The method of claim 1 , wherein measuring the operating margin comprises:

measuring power consumption of an I/O exchange.

12. The method of claim 1 , wherein measuring the operating margin comprises:

measuring an eye width of an output signal curve.

13. The method of claim 1 , wherein measuring the operating margin comprises:

measuring an eye height of an output signal curve.

14. The method of claim 1 , wherein measuring the operating margin comprises:

measuring an operating frequency of the memory subsystem.

15. The method of claim 1 , wherein executing the search function comprises:

performing an n-dimensional search, n 1-dimensional searches, a linear fit search, a quadratic fit search, a steepest descent search, or a curve fitting search.

16. The method of claim 1 , wherein executing the search function further comprises:

correlating multiple test results to compensate for noise.

17. An apparatus comprising:

a host hardware platform including a processor;

a test system embedded in a memory controller to perform a search for parameter settings for a memory device, including to establish respective settings for each of multiple different I/O (input/output) circuit parameters for a target I/O performance characteristic for I/O with the memory device:

set a value for each I/O circuit parameter, generate test traffic with a test engine embedded in the memory controller to stress test the memory device, and measure an operating margin for the I/O performance characteristic,

repeatedly set a new value for at least one of the I/O circuit parameters and generate test traffic with the test engine to repeatedly stress test the memory device so that a plurality of measurements with different I/O circuit parameters is made;

execute a search function to determine values for each I/O circuit parameter at which the operating margin meets a minimum threshold, wherein, the search function is to extrapolate from the plurality of measurements to a worst case condition, and

set runtime values for the I/O circuit parameters based on the execution of the search function.

18. The apparatus of claim 17 , wherein the target I/O performance characteristic comprises:

power consumption of a memory subsystem that includes the memory controller and the memory device, operating frequency of the memory subsystem, or I/O latency of the memory subsystem.

19. The apparatus of claim 17 , wherein the test system is to set the value for the I/O circuit parameter including

set one of an output resistance of a transmitter, or an input resistance of a receiver, set a slew rate of an output driver or a value of an equalization stage, set a value of a turnaround time, or set parameters of a receive circuit separately from a transmit circuit.

20. The apparatus of claim 17 , wherein the test system is to measure the operating margin including

measure power consumption of an I/O exchange, measure an eye width of an output signal curve, measure an eye height of an output signal curve, or measure frequency.

21. The apparatus of claim 17 , wherein the test system is to execute the search function including

perform an n-dimensional search, n 1-dimensional searches, a linear fit search, a quadratic fit search, a steepest descent search, or a curve fitting search.

22. An electronic device comprising:

a host hardware platform including a processor;

a memory subsystem on the host hardware platform including a memory controller and a memory device; and

a test system embedded in the memory subsystem to perform a search for parameter settings, including to establish respective settings for each of multiple different I/O (input/output) circuit parameters for a target I/O performance characteristic for I/O with the memory device:

set a value for each I/O circuit parameter, generate test traffic with a test engine embedded in the memory controller to stress test the memory device, and measure an operating margin for the I/O performance characteristic, and

repeatedly set a new value for at least one of the I/O circuit parameters and generate test traffic with the test engine to repeatedly stress test the memory device so that a plurality of measurements with different I/O circuit parameters is made;

execute a search function to determine values for each I/O circuit parameter at which the operating margin meets a minimum threshold, and performance of at least one of the I/O circuit parameters is increased, wherein, the search function is to extrapolate from the plurality of measurements to a worst case condition, and

set runtime values for the I/O circuit parameters based on the execution of the search function.

23. The electronic device of claim 22 , wherein the target I/O performance characteristic comprises:

power consumption of the memory subsystem, operating frequency of the memory subsystem, or I/O latency of the memory subsystem.