Memory system and data transmission method
View Patent ↗A memory system of a high-speed operation can be realized by reducing an influence of reflection signals etc. caused by branching and impedance mismatching in various wirings between a memory controller and a memory module, and an influence due to transmission delays of data, command/address, and clocks in the memory module. To this end, a memory system comprises a memory controller and a memory module mounted with DRAMs. A buffer is mounted on the memory module. The buffer and the memory controller are connected to each other via data wiring, command/address wiring, and clock wiring. The DRAMs and the buffer on the memory module are connected to each other via internal data wiring, internal command/address wiring, and internal cock wiring. The data wiring, the command/address wiring, and the clock wiring may be connected to buffers of other memory modules in cascade. Between the DRAMs and the buffer on the memory module, high-speed data transmission is implemented using data phase signals synchronous with clocks.
1. A memory system comprising:
a substrate;
a plurality of memory chips mounted over the substrate, the plurality of memory chips receiving a first signal and a second signal;
a memory buffer mounted over the substrate, the memory buffer including a detection circuit which detects a skew between the first signal and the second signal, and the memory buffer including an adjustment circuit which adjusts a relationship between the first signal and the second signal based on the skew;
a first wiring configured to commonly couple each of the plurality of memory chips for transferring the first signal to the each of the plurality of memory chips in common; and
a plurality of second wirings corresponding with the plurality of memory chips, each first end of the plurality of second wirings configured to couple to an associated one of the plurality of memory chips independently for transferring the second signal to an associated one of the plurality of memory chips.
2. The memory system according to claim 1 , wherein each second end of the plurality of second wirings is configured to couple to the memory buffer.
3. The memory system according to claim 1 , wherein the first signal is a clock signal or a command/address signal, the second signal includes a date signal or a timing signal being synchronized with the date signal.
4. The memory system according to claim 1 , further comprising an output circuit supplying a third signal based on the first signal or the second signal from each of the plurality of the memory chips to a memory controller.
5. The memory system according to claim 1 , wherein selected one of the plurality of memory chips based on the first and second signals outputs a third signal and a fourth signal to the memory buffer, the detection circuit in the memory buffer which detects a skew between the third and fourth signals, and the adjustment circuit in the memory buffer which adjust a relationship between the third signal and the fourth signal based on the skew.
6. The memory system according to claim 1 , wherein the plurality of memory chips includes a first plurality of memory chips mounted over a first area of the substrate and a second plurality of memory chips mounted over a second area of the substrate, and the memory buffer mounted over a third area of the substrate between the first area and the second area.
7. The memory system according to claim 1 , wherein the memory buffer receives command/address signals and data signals from a memory controller, and outputs the first signal based on the command/address signals and the second signal based on the data signals.
8. The memory module according to claim 2 , wherein the first signal is a clock signal or a command/address signal, the second signal include a date signal or a timing signal being synchronized with the date signal.
9. The memory module according to claim 1 , further comprising an output circuit supplying a third signal based on the first signal or the second signal.
10. A memory system comprising:
a substrate;
a plurality of memory chips mounted over the substrate;
the plurality of memory chips receiving a first signal and a second signal;
a memory buffer mounted over the substrate;
a first wiring configured to commonly couple each of the plurality of memory chips for transferring the first signal to the each of the plurality of memory chips in common;
a plurality of second wirings corresponding with the plurality of memory chips, each first end of the plurality of second wirings configured to couple to an associated one of the plurality of memory chips independently for transferring the second signal to an associated one of the plurality of memory chips, each second end of the plurality of second wirings is configured to couple to the memory buffer; and
a memory controller coupled to the memory buffer and supplying the memory buffer with a plurality of signals, the memory buffer generating the first signal and the second signal based on the plurality of signals;
wherein at least one of the memory buffer and the memory controller includes a detection circuit which detects a skew between the first signal and the second signal and an adjustment circuit which adjust a relationship between the first signal and the second signal based on the skew.
11. The memory system according to claim 10 , wherein the first signal is a signal based on a clock signal or a command/address signal supplied from the memory controller as a part of the plurality of signals, the second signal is a date signal or a timing signal being synchronized with the date signal supplied from the memory controller as a part of the plurality of signals.
12. The memory system according to claim 10 , wherein each of the memory controller and the memory buffer includes a detection circuit which detects a skew between the first signal and the second signal and an adjustment circuit which adjust a relationship between the first signal and the second signal based on the skew.
13. A memory system comprising:
a substrate;
a plurality of memory chips mounted over the substrate;
the plurality of memory chips receiving a first signal and a second signal;
a memory buffer mounted over the substrate;
a first wiring configured to commonly couple each of the plurality of memory chips for transferring the first signal to the each of the plurality of memory chips in common; a plurality of second wirings corresponding with the plurality of memory chips, each first end of the plurality of second wirings configured to couple to an associated one of the plurality of memory chips independently for transferring the second signal to an associated one of the plurality of memory chips, each second end of the plurality of second wirings is configured to couple to the memory buffer; and
a memory controller coupled to the memory buffer and supplying the memory buffer with a plurality of signals, the memory buffer generating the first signal and the second signal based on the plurality of signals;
wherein each of the memory buffer and the memory controller includes a detection circuit which detects a skew between the first signal and the second signal and an adjustment circuit which adjust a relationship between the first signal and the second signal based on the skew.
14. The memory system according to claim 13 , wherein the first signal is a signal based on a clock signal or a command/address signal supplied from the memory controller as a part of the plurality of signals, the second signal is a date signal or a timing signal being synchronized with the date signal supplied from the memory controller as a part of the plurality of signals.