High voltage switching devices and process for forming same
View Patent ↗The present invention relates to various switching device structures including Schottky diode, P-N diode, and P-I-N diode, which are characterized by low defect density, low crack density, low pit density and sufficient thickness (>2.5 um) GaN layers of low dopant concentration (<1E16 cm −3 ) grown on a conductive GaN layer. The devices enable substantially higher breakdown voltage on hetero-epitaxial substrates (<2 KV) and extremely high breakdown voltage on homo-epitaxial substrates (>2 KV).
1. A microelectronic device structure, comprising:
a first GaN layer having a top surface characterized by a dislocation defect density of not more than 5×10 6 /cm 2 ;
a second, conductive GaN layer overlying said first GaN layer;
a third GaN layer overlying said second, conductive GaN layer, said third GaN layer having a dopant concentration of not more than 1×10 16 /cm 3 and a thickness of at least 2.5 μm; and
at least one metal contact over said third GaN layer, forming a metal-to-semiconductor junction therewith.
2. The microelectronic device structure of claim 1 , having a breakdown voltage of at least 320V.
3. The microelectronic device structure of claim 1 , further comprising a substrate, wherein the first GaN layer is overlying the substrate.
4. The microelectronic device structure of claim 3 , wherein the substrate comprises a foreign substrate, and the microelectronic device structure further comprises a nucleation buffer layer disposed between the first GaN layer and the foreign substrate.
5. The microelectronic device structure of claim 4 , wherein the foreign substrate comprises a material selected from the group consisting of sapphire, Si, and SiC.
6. The microelectronic device structure of claim 1 , wherein the third GaN layer is less than 20 μm in thickness.
7. The microelectronic device structure of claim 1 , wherein the third GaN layer is less than 50 μm in thickness.
8. The microelectronic device structure of claim 1 , wherein the second, conductive GaN layer is doped with a dopant for strain relaxation.
9. The microelectronic device structure of claim 1 , wherein the second, conductive GaN layer is doped with germanium.
10. The microelectronic device structure of claim 1 , wherein the first GaN layer has a thickness of about 0.6 μm, and wherein the second, conductive GaN layer has a thickness of from about 0.5 μm to about 2 mm and has a dopant concentration of about 1.5×10 19 /cm 3 .
11. The microelectronic device structure of claim 1 , wherein the second, conductive GaN layer comprises a first conductive GaN sub-layer of a first dopant concentration and comprises a second GaN sub-layer of a second dopant concentration, wherein said first conductive GaN sub-layer is adjacent to the first GaN layer, wherein said second conductive GaN sub-layer is adjacent to the third GaN layer, and wherein the first dopant concentration is lower than said second dopant concentration.
12. The microelectronic device structure of claim 1 , comprising a Schottky diode selected from the group consisting of mesa-type Schottky diodes and planar-type Schottky diodes.
13. A microelectronic device structure comprising:
a first GaN layer having a top surface characterized by a dislocation defect density of not more than 5×10 6 /cm2;
a second GaN layer having a dopant concentration of not more than 1×10 15 /cm 3 and a thickness of more than 10 μm formed over said first GaN layer;
a third GaN layer of p-type conductivity, formed over said second GaN layer; and
at least one metal contact overlying said third GaN layer.
14. The microelectronic device structure of claim 13 , wherein the first GaN layer is of n-type conductivity.
15. The microelectronic device structure of claim 13 , wherein the first GaN layer comprises a free-standing GaN structure.
16. The microelectronic device structure of claim 13 , comprising a Schottky diode selected from the group consisting of mesa-type Schottky diodes and planar-type Schottky diodes.
17. A microelectronic device structure, comprising:
(a) a first GaN layer;
(b) a second GaN layer of n-type conductivity, overlying said first GaN layer;
(c) a third GaN layer overlying said second GaN layer of n-type conductivity, said third GaN layer having a dopant concentration of not more than about 1×10 16 /cm 3 and a thickness of at least about 2.5 μm;
(d) a fourth GaN layer of p-type conductivity, formed over said third GaN layer; and
(e) at least one metal contact overlying said fourth GaN layer.
18. The microelectronic device structure of claim 17 , wherein the first GaN layer has a dopant concentration of not more than about 1×10 16 /cm 3 .
19. The microelectronic device structure of claim 17 , wherein the first GaN layer has a top surface characterized by a dislocation defect density of not more than 5×10 6 /cm 2 .
20. The microelectronic device structure of claim 17 , further comprising a substrate, wherein the first GaN layer is overlying the substrate.
21. The microelectronic device structure of claim 20 , wherein the substrate comprises a foreign substrate, and the microelectronic device structure further comprises a nucleation buffer layer disposed between the first GaN layer and the foreign substrate.
22. The microelectronic device structure of claim 21 , wherein said foreign substrate comprises a material selected from the group consisting of sapphire, Si, and SiC.
23. The microelectronic device structure of claim 17 , wherein the third GaN layer is less than 20 μm in thickness.
24. The microelectronic device structure of claim 17 , wherein the third GaN layer is less than 50 μm in thickness.
25. The microelectronic device structure of claim 17 , wherein the second GaN layer of n-type conductivity is doped with a strain-reducing dopant.
26. The microelectronic device structure of claim 17 , wherein the second GaN layer of n-type conductivity is doped with germanium.
27. The microelectronic device structure of claim 17 , wherein the first GaN layer has a thickness of about 0.6 μm, and wherein the second, conductive GaN layer has a thickness of from about 0.5 μm to about 2 mm and has a dopant concentration of about 1.5×10 19 /cm 3 .
28. The microelectronic device structure of claim 17 , wherein the second, conductive GaN layer comprises a first conductive GaN sub-layer of a first dopant concentration and comprises a second GaN sub-layer of a second dopant concentration, wherein said first conductive GaN sub-layer is adjacent to the first GaN layer, wherein said second conductive GaN sub-layer is adjacent to the third GaN layer, and wherein the first dopant concentration is lower than said second dopant concentration.
29. The microelectronic device structure of claim 17 , comprising a Schottky diode selected from the group consisting of mesa-type Schottky diodes and planar-type Schottky diodes.