Power semiconductor devices, structures, and related methods
View Patent ↗Power semiconductor devices, and related methods, where majority carrier flow is divided into paralleled flows through two drift regions of opposite conductivity types.
1. A semiconductor device, comprising:
an n-type semiconductor source region;
a p-type semiconductor body region;
a gate electrode, which is capacitively coupled to invert a portion of said body region;
a semiconductor drift region which includes both n-type and p-type semiconductor portions electrically connected in parallel;
immobile positive point charges which are capacitively coupled to jointly invert parts of said p-type drift region portions; and
an n-type semiconductor drain region;
wherein said body region is interposed between said source region and said drift region;
and wherein said drift region is interposed between said body region and said drain region;
whereby, in the ON state, electrons flow both through said n-type portions and said p-type portions of said drift region in parallel.
2. The device of claim 1 , wherein said source, body, drain and drift regions are silicon.
3. The device of claim 1 , wherein said immobile electrostatic charges are cesium ions.
4. The device of claim 1 , wherein said gate electrode lies entirely inside a trench.
5. The device of claim 1 , wherein said immobile electrostatic charges are ions in a dielectric material in a trench.
6. A semiconductor device, comprising:
a first-conductivity-type semiconductor source region;
a second-conductivity-type semiconductor body region;
a generally planar gate electrode, which is capacitively coupled to invert a portion of said body region to define a predominantly horizontal channel therein;
a semiconductor drift region which includes both first-conductivity-type and second-conductivity-type semiconductor pillars in parallel;
immobile electrostatic charge which is capacitively coupled to invert parts of said second-conductivity-type drift region portions; and
a first-conductivity-type semiconductor drain region;
wherein said body region is interposed between said source region and said drift region;
and wherein said drift region is interposed between said body region and said drain region;
and wherein, in the ON state, majority carriers flow both through said first-conductivity-type and said second-conductivity-type pillars in parallel.
7. The device of claim 6 , wherein said generally horizontal channel adjoins said drift region at locations which are more nearly aligned with said first-conductivity-type pillars than with said second-conductivity-type pillars.
8. The device of claim 6 , wherein said generally horizontal channel adjoins said drift region at locations which are more nearly aligned with said second-conductivity-type pillars than with said first-conductivity-type pillars.
9. The device of claim 6 , wherein said immobile electrostatic charge is provided by cesium ions.
10. The device of claim 6 , wherein said first-conductivity-type source region is n-type, and said majority carriers are electrons.
11. The device of claim 6 , wherein said source, body, drain and drift regions are silicon.
12. The device of claim 6 , wherein said immobile electrostatic charge consists of point charges.
13. The device of claim 6 , wherein said immobile electrostatic charge is provided by ions in dielectric material and/or by ions at a dielectric/semiconductor interface.
14. The device of claim 6 , wherein said immobile electrostatic charge is provided by ions in dielectric material in a trench.
15. A semiconductor device, comprising:
an n-type semiconductor source region;
a p-type semiconductor body region;
a planar gate electrode, which is capacitively coupled to invert a portion of said body region to define a predominantly horizontal channel therein;
a semiconductor drift region which includes both n-type and p-type semiconductor pillars in parallel;
immobile electrostatic charge which is capacitively coupled to invert parts of said p-type drift region portions; and
an n-type semiconductor drain region;
wherein said body region is interposed between said source region and said drift region;
and wherein said drift region is interposed between said body region and said drain region;
and wherein, in the ON state, majority carriers flow both through said n-type and said p-type pillars in parallel.
16. The device of claim 15 , wherein said source, body, drain and drift regions are silicon.
17. The device of claim 15 , wherein said immobile electrostatic charge consists of cesium ions.
18. The device of claim 15 , wherein said immobile electrostatic charge consists of point charges.
19. The device of claim 15 , wherein said immobile electrostatic charge is provided by ions in dielectric material and/or by ions at a dielectric/semiconductor interface.
20. The device of claim 15 , wherein said immobile electrostatic charge is provided by ions in dielectric material in a trench.