IP Library Granted Patent US 8,710,499
Granted Patent B2
US 8,710,499 · App. 13/770,120 · Granted Apr 29, 2014

Transistor and display device

Inventors: Shunpei Yamazaki (Setagaya, JP); Toshinari Sasaki (Atsugi, JP); Junichiro Sakata (Atsugi, JP); Masashi Tsubuku (Atsugi, JP)
Assignee: Semiconductor Energy Laboratory Co., Ltd.
View Patent ↗
Loading inventors, assignments & file history…
Monitor This Case
Get email alerts when status or documents change.
Order Certified Copies
Most orders are placed with the USPTO same day — all within 24 business hours.
Order via The Patent Place →
Pre-filled with this patent's details
Quick Facts
Patent No.
US 8,710,499
App. No.
13/770,120
Granted
Apr 29, 2014
Kind
B2
Abstract

It is an object to manufacture a highly reliable display device using a thin film transistor having favorable electric characteristics and high reliability as a switching element. In a bottom gate thin film transistor including an amorphous oxide semiconductor, an oxide conductive layer having a crystal region is formed between an oxide semiconductor layer which has been dehydrated or dehydrogenated by heat treatment and each of a source electrode layer and a drain electrode layer which are formed using a metal material. Accordingly, contact resistance between the oxide semiconductor layer and each of the source electrode layer and the drain electrode layer can be reduced; thus, a thin film transistor having favorable electric characteristics and a highly reliable display device using the thin film transistor can be provided.

Claims (43)

1. A transistor comprising:

a gate electrode layer;

an oxide semiconductor layer adjacent to the gate electrode layer with a gate insulating layer therebetween;

a source electrode layer adjacent to the oxide semiconductor layer with an oxide conductive layer therebetween; and

a drain electrode layer adjacent to the oxide semiconductor layer with the oxide conductive layer therebetween,

wherein the oxide conductive layer includes a microcrystalline region, and

wherein a peak of a desorption constituent, which is derived from moisture, is not shown in a spectrum of the oxide semiconductor layer, which is shown with thermal desorption spectroscopy in a temperature range of greater than or equal to 200° C. and less than or equal to 350° C.

2. The transistor according to claim 1 , wherein the oxide semiconductor layer is amorphous.

3. The transistor according to claim 1 , wherein the source electrode layer and the drain electrode layer are formed using a film including an element selected from Al, Cr, Cu, Ta, Ti, Mo, and W as its main component or an alloy film thereof.

4. The transistor according to claim 1 , further comprising an oxide insulating layer between the oxide semiconductor layer and the oxide conductive layer.

5. The transistor according to claim 4 , wherein the oxide insulating layer is formed by a sputtering method using silicon oxide, silicon nitride oxide, aluminum oxide, or aluminum oxynitride.

6. The transistor according to claim 1 , wherein the oxide conductive layer is formed using one kind selected from indium oxide, an indium oxide-tin oxide alloy, an indium oxide-zinc oxide alloy, zinc oxide, zinc aluminum oxide, zinc aluminum oxynitride, and zinc gallium oxide.

7. A transistor comprising:

a gate electrode layer;

a gate insulating layer over the gate electrode layer;

an oxide semiconductor layer over the gate insulating layer;

an oxide conductive layer over the oxide semiconductor layer;

a source electrode layer over the oxide conductive layer; and

a drain electrode layer over the oxide conductive layer;

wherein the oxide conductive layer includes a microcrystalline region, and

wherein a peak of a desorption constituent, which is derived from moisture, is not shown in a spectrum of the oxide semiconductor layer, which is shown with thermal desorption spectroscopy in a temperature range of greater than or equal to 200° C. and less than or equal to 350° C.

8. The transistor according to claim 7 , wherein the oxide semiconductor layer is amorphous.

9. The transistor according to claim 7 , wherein the source electrode layer and the drain electrode layer are formed using a film including an element selected from Al, Cr, Cu, Ta, Ti, Mo, and W as its main component or an alloy film thereof.

10. The transistor according to claim 7 , further comprising an oxide insulating layer between the oxide semiconductor layer and the oxide conductive layer.

11. The transistor according to claim 10 , wherein the oxide insulating layer is formed by a sputtering method using silicon oxide, silicon nitride oxide, aluminum oxide, or aluminum oxynitride.

12. The transistor according to claim 7 , wherein the oxide conductive layer is formed using one kind selected from indium oxide, an indium oxide-tin oxide alloy, an indium oxide-zinc oxide alloy, zinc oxide, zinc aluminum oxide, zinc aluminum oxynitride, and zinc gallium oxide.

13. A display device comprising:

a pixel portion over a substrate; and

a driver circuit over the substrate and comprising a transistor;

the transistor comprising:

a gate electrode layer;

a gate insulating layer over the gate electrode layer;

an oxide semiconductor layer over the gate insulating layer;

an oxide conductive layer over the oxide semiconductor layer;

a source electrode layer over the oxide conductive layer; and

a drain electrode layer over the oxide conductive layer;

wherein the oxide conductive layer includes a microcrystalline region, and

wherein a peak of a desorption constituent, which is derived from moisture, is not shown in a spectrum of the oxide semiconductor layer, which is shown with thermal desorption spectroscopy in a temperature range of greater than or equal to 200° C. and less than or equal to 350° C.

14. The transistor according to claim 13 , wherein the oxide semiconductor layer is amorphous.

15. The transistor according to claim 13 , wherein the source electrode layer and the drain electrode layer are formed using a film including an element selected from Al, Cr, Cu, Ta, Ti, Mo, and W as its main component or an alloy film thereof.

16. The transistor according to claim 13 , further comprising an oxide insulating layer between the oxide semiconductor layer and the oxide conductive layer.

17. The transistor according to claim 16 , wherein the oxide insulating layer is formed by a sputtering method using silicon oxide, silicon nitride oxide, aluminum oxide, or aluminum oxynitride.

18. The transistor according to claim 13 , wherein the oxide conductive layer is formed using one kind selected from indium oxide, an indium oxide-tin oxide alloy, an indium oxide-zinc oxide alloy, zinc oxide, zinc aluminum oxide, zinc aluminum oxynitride, and zinc gallium oxide.

Priority Claims (1)
JP 2009-204801 · Sep 4, 2009 · national
Continuity (2)
Continuation 12869278 · Aug 26, 2010
Related Publication 20130153910A1 · Jun 20, 2013