Processor simulation environment
In a method of simulating a processor system by running code that simulates the system on a host processor, code is translated at run time to a form required by the host processor. All instructions are mapped to a native instruction set of the host using two or more different code dictionaries: the translated instructions are mapped to multiple and different dictionaries dependent on the execution privilege level or mode of the simulated processor. If an instruction is encountered during runtime that changes the mode of the processor the code dictionary is switched to use the dictionary associated with the new mode. The different modes require different instruction mappings to the native instruction set of the host using different models that more accurately represent the behavior of the system code and hardware in the system being simulated.
1. A method of simulating a processor system by running system code that simulates the system on a host processor, in which the system code has two or more execution privilege levels or modes and is translated at run time to a form required by the host processor; comprising the steps of:
(i) selecting a specific code dictionary from a set of two or more different code dictionaries, each execution privilege level or mode being associated with a different code dictionary;
(ii) mapping all instructions to a native instruction set of the host processor using the code dictionary selected from the set of two or more different code dictionaries,
in which, in a first mode, all instructions that are outside a SPECULATE/COMMIT region are mapped to a native instruction set of the host using the first code dictionary; and in which, in a second mode, all instructions within a SPECULATE/COMMIT region are mapped to the native instruction set of the host using a second code dictionary.
2. The method of claim 1 in which, if an instruction is encountered during runtime that changes the mode of the host processor, the code dictionary is switched to use the dictionary associated with the new mode.
3. The method of claim 1 in which the different modes require different instruction mappings to the native instruction set of the host using different models that more accurately represent the behaviour of the system code and hardware in the processor system being simulated.
4. The method of claim 1 , in which a mode, associated with a specific dictionary, is a user mode, being a restricted mode and provides access to a subset of the resources of the processor and system.
5. The method of claim 1 , in which a mode, associated with a specific dictionary, is a system mode, being an unrestricted mode and allows the processor to access all of the resources of the processor and system.
6. The method of claim 1 , in which a mode, associated with a specific dictionary, is a hypervisor mode.
7. The method of claim 1 , in which a mode, associated with a specific dictionary, is a virtual memory mode.
8. The method of claim 1 , in which a mode, associated with a specific dictionary, is a physical memory mode.