Apparatus and methods for forming a memory cell using charge monitoring
View Patent ↗Apparatuses and methods of forming a memory cell is described. In one such method, a forming charge applied to a memory cell, such as a Resistive RAM (RRAM) memory cell, is monitored to determine the progress of the forming the cell. If the cell is consuming charge too slowly, a higher voltage can be applied. If the cell is consuming charge too quickly, a lower voltage can be applied. The charge may be monitored by charging a capacitor to a certain level, then monitoring the discharge rate of the capacitor though the cell. The monitoring may use comparators to measure the charge. The monitoring may also use an analog to digital converter to perform the monitoring.
1. A method comprising:
applying a voltage to a resistive memory cell in a forming stage prior to and separate from first programming the resistive memory cell;
monitoring a forming charge applied to the resistive memory cell via the voltage; and
adjusting the voltage based on the charge being monitored.
2. The method of claim 1 wherein applying a voltage to the resistive memory cell comprises charging a capacitor having a capacitance and discharging the capacitor through the resistive memory cell; and wherein monitoring the forming charge comprises measuring a change in voltage across the capacitor.
3. The method of claim 1 wherein adjusting the voltage comprises:
raising the voltage when the monitored charge is lower than a certain value.
4. The method of claim 1 wherein adjusting the first voltage comprises:
lowering the voltage when the monitored charge is higher than a certain predetermined value.
5. An apparatus comprising:
a resistive memory cell;
a capacitor;
a comparator with a first input coupled to the capacitor, a second input coupled to a reference voltage node and an output;
a transistor coupled to the capacitor and to the resistive memory cell; and
control logic coupled to the output of the comparator, wherein said control logic is configured to adjust a voltage applied to a gate of the transistor based on the output of the comparator to form the resistive memory cell in a forming stage prior to and separate from first programming the resistive memory cell.
6. The apparatus of claim 5 wherein said control logic is configured to adjust the voltage applied to the gate of the transistor responsive to a voltage at the first input of the first comparator becoming lower than a voltage at the second input of the first comparator.
7. The apparatus of claim 5 , wherein the comparator comprises a first comparator and the reference voltage node comprises a first reference voltage node, and further comprising:
a second comparator with a first input coupled to the capacitor, a second input coupled to a second reference voltage node, and an output, wherein the output of the second comparator is coupled to the control logic, and wherein during operation a voltage at the second reference voltage node is lower than a voltage at the first reference voltage node.
8. The apparatus of claim 7 wherein:
the control logic is configured to adjust the voltage applied to the gate of the transistor to a first level responsive to the voltage at the first input of the first comparator becoming lower than the voltage at the second input of the first comparator; and
the control logic is further configured to adjust the voltage applied to the gate of the transistor to a second level responsive to a voltage at the first input of the second comparator becoming lower than a voltage at the second input of the second comparator.
9. The apparatus of claim 5 wherein the resistive memory cell comprises a resistive random access memory (RRAM) cell including a binary-transition metal-oxide based material, a copper-based material, or a chalcogenide.
10. The apparatus of claim 5 wherein the transistor is configured in a source follower configuration.
11. The apparatus of claim 5 wherein:
the capacitor has a capacitance in the range of 100 femtofarads to 1 nanofarad.
12. The apparatus of claim 5 further comprising:
a switch coupled to the capacitor; wherein the switch is further coupled to the control logic; and further wherein
the control logic is configured to operate the switch to begin and end a charging of the capacitor.
13. An apparatus comprising:
a resistive memory cell;
a capacitor;
a transistor coupled to the resistive memory cell and to the capacitor;
an analog to digital converter (ADC) coupled to the capacitor, the ADC having an output based on a voltage of the capacitor; and
control logic coupled to the output of the ADC, wherein said control logic is configured to adjust a voltage applied to a gate of the transistor based on the output of the ADC to form the resistive memory cell in a forming stage prior to and separate from first programming the resistive memory cell.
14. The apparatus of claim 13 wherein said control logic is configured to adjust the voltage applied to the gate of the transistor responsive to the output of the ADC indicating that the voltage of the capacitor has reached a first level.
15. The apparatus claim 14 wherein said control logic being configured to adjust the voltage comprises the control logic being configured to lower the voltage applied to the gate of the transistor.
16. The apparatus of claim 14 wherein said control logic is configured to adjust the voltage applied to the gate of the transistor responsive to the output of the ADC indicating that the voltage of the capacitor has reached a second level.
17. The apparatus of claim 13 wherein the memory cell comprises a resistive random access memory (RRAM) cell including a binary-transition metal-oxide based material, a copper-based material, or a chalcogenide.
18. The apparatus of claim 13 wherein:
the transistor is configured in a source follower configuration.
19. The apparatus of claim 13 further comprising:
a switch coupled to the capacitor; wherein the switch is further coupled to the control logic; and further wherein
the control logic is configured to operate the switch to begin and end a charging of the capacitor.
20. A method comprising:
charging a capacitor;
coupling the charged capacitor to a resistive memory cell in a forming stage prior to and separate from first programming the resistive memory cell;
monitoring a forming charge applied to the resistive memory cell responsive to coupling the charged capacitor to the memory cell; and
decoupling the charged capacitor from the resistive memory cell responsive to the monitoring.
21. The method of claim 20 further comprising:
controlling the charging of the capacitor based on the monitored charge.
22. A method comprising:
charging a capacitor;
discharging the capacitor through a transistor coupled to a resistive memory cell in a forming stage prior to and separate from first programming the resistive memory cell;
monitoring the charge that was discharged to the resistive memory cell; and
determining if the charge is sufficient to form the resistive memory cell.
23. The method of claim 22 wherein charging a capacitor comprises:
coupling the capacitor to a voltage source for a certain amount of time; and
de-coupling the capacitor from the voltage source after the certain amount of time.
24. The method of claim 22 further comprising de-coupling the resistive memory cell from the capacitor responsive to determining that the charge is sufficient to form the resistive memory cell.