IP Library › Granted Patent US 9,209,395

Granted Patent B2

US 9,209,395 · App. 13/776,354 · Granted Dec 8, 2015

Variable resistance memory with lattice array using enclosing transistors

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Quick Facts

Patent No.: US 9,209,395
App. No.: 13/776,354
Granted: Dec 8, 2015
Kind: B2

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Abstract

A variable resistance memory array, programming a variable resistance memory element and methods of forming the array. A variable resistance memory array is formed with a plurality of word line transistors surrounding each phase change memory element. To program a selected variable resistance memory element, all of the bitlines are grounded or biased at the same voltage. A top electrode select line that is in contact with the selected variable resistance memory element is selected. The word line having the word line transistors surrounding the selected variable resistance memory element are turned on to supply programming current to the element. Current flows from the selected top electrode select line through the variable resistance memory element into the common source/drain region of the surrounding word line transistors, across the transistors to the nearest bitline contacts. The word lines are patterned in various lattice configurations.

Claims (83)

1. A method of forming a memory array comprising:

forming a plurality of word lines over a substrate to form groups of at least three transistors, each group sharing one of a plurality of common source/drain regions;

forming a phase change memory element electrically coupled to a common source/drain region shared by a first group of transistors;

forming a bitline contact electrically coupled to a common source/drain region shared by a second group of transistors, wherein the common source/drain region coupled to the bitline contact is electrically coupled to the common/source drain region coupled to the phase change memory element through a transistor common to the first and second groups of transistors; and

forming a top electrode select line electrically coupled to the phase change memory element,

wherein forming the plurality of word lines further comprises:

forming a first plurality of isolated gate stacks along a first direction over the substrate, a second plurality of isolated gate stacks along a second direction over the substrate, and a third plurality of isolated gate stacks along a third direction over the substrate, wherein the first, second, and third directions comprise a hexagonal array pattern; and

forming a first electrical connection between the first plurality of gate stacks to form the first plurality of word lines, a second electrical connection between the second plurality of gate stacks to form the second plurality of word lines, and a third electrical connection between the third plurality of gate stacks to form the third plurality of word lines.

2. A method of forming a memory array comprising:

forming a plurality of word lines to form groups of at least three transistors, each group sharing one of a plurality of common source/drain regions;

forming a phase change memory element electrically coupled to a common source/drain region shared by a first group of transistors;

forming a bitline contact electrically coupled to a source/drain region of one of the transistors of the first group, which is electrically coupled to the common source/drain region; and

forming a top electrode select line in contact with the phase change memory element,

wherein forming the plurality of word lines comprises forming the plurality of word lines into a plurality of substantially triangle word line shapes.

3. A method of forming a memory array comprising:

forming a first plurality of word lines over a substrate extending in a first direction;

forming a second plurality of word lines electrically isolated from the first plurality of word lines over the substrate extending in a second direction;

forming a plurality of source/drain regions on opposite sides of each of the first and second plurality of word lines such that the first and second word lines define a group of transistors which share common source/drain regions;

forming a phase change memory element electrically coupled to a first common source/drain region of one of the transistors of a first group;

forming a bitline contact electrically coupled to a second common source/drain region of the one of the transistors of the first group;

forming a top electrode select line electrically coupled to the phase change memory element; and

forming a bitline electrically coupled to the bitline contact;

wherein, the first and second common source/drain regions are electrically coupled through the one transistor of the first group.

4. The method of claim 3 ,

wherein the first and second plurality of word lines are formed as isolated gate stacks which extend in first and second directions;

the method further comprising;

electrically coupling the isolated gate stacks arranged in the first direction to form the first plurality of word lines; and

electrically coupling the isolated gate stacks arranged in the second direction to form the second plurality of word lines.

5. The method of claim 3 , further comprising;

etching an array of square patterns into the substrate; and

forming a shallow trench isolation regions in the substrate by filling the etched square patterns with oxide;

wherein the first and second plurality of word lines are formed over the substrate to intersect over the shallow trench isolation regions.

6. The method of claim 3 , wherein forming the first plurality of word lines comprises forming a first array of parallel word lines on the substrate by a recessed transistor process.

7. The method of claim 3 , wherein the first plurality of word lines are perpendicular to the second plurality of word lines.

8. The method of claim 3 , wherein the top electrode select line is diagonal to either the first or second plurality of word lines.

9. The method of claim 3 , wherein the top electrode select line is wavy.

10. The method of claim 3 , wherein the bitline is diagonal to either the first or second plurality of word lines.

11. The method of claim 3 , further comprising:

forming a nitride spacers on either the first or second plurality of word lines before forming the common source/drain regions.

12. A method of claim 3 , further comprising:

forming a third plurality of word lines electrically isolated from the first and second plurality of word lines over the substrate extending in a third direction; and

forming a plurality of source/drain regions on the substrate on the opposite sides of the third plurality of word lines such that the first, second and third word lines define groups of transistors which share common source/drain regions.

13. The method of claim 12 , wherein forming the second plurality of word lines comprises forming the second plurality of word lines at a substantially 60 degree angle to the first plurality of word lines.

14. The method of claim 12 , wherein forming the third plurality of word lines comprises forming the third plurality of word lines at a substantially negative 60 degree angle to the first plurality of word lines.

15. A method of forming a memory array comprising:

forming a plurality of word lines over a substrate;

forming a plurality of source/drain regions on the substrate on opposite sides of the plurality of word lines, wherein

the word lines and the source/drain regions formed on the opposite sides thereof form a plurality of transistors, and

the source/drain regions are shared by the plurality of transistors;

forming a phase change memory element electrically coupled to a first source/drain region of one of the plurality of transistors;

forming a bitline contact electrically coupled to a second source/drain region of the one of the plurality of transistors;

forming a top electrode select line electrically coupled to the phase change memory element; and

forming a bitline electrically coupled to the bitline contact;

wherein the word lines are formed over the substrate such that a group of transistors surround the first source/drain region;

wherein the bitline is parallel to and does not overlap with the word lines;

wherein the word lines form ladder shape patterns over the substrate;

wherein the first source/drain region is formed within an enclosed area of a ladder shape pattern; and

wherein the ladder shape is a round ladder shape.

16. A method of forming a memory array comprising: