Memory modules and devices supporting configurable data widths
Described are memory apparatus organized in physical banks and including configurable data control circuit to support multiple data-width configurations. Relatively narrow width configurations load fewer sense amplifiers, resulting in reduced power usage for relatively narrow memory configurations. Also described are memory controllers that convey configuration value to configurable memory apparatus and support point-to-point data buffers for multiple width configurations.
1. An integrated-circuit memory device comprising:
an input to receive memory-width configuration value;
data terminals to exchange data with another device;
a plurality of physical banks, each physical bank including columns of memory cells coupled to corresponding sense amplifiers; and
a data control circuit coupling the physical banks with the data terminals, the data control circuit supporting first and second width configurations responsive to the configuration value;
wherein:
in the first width configuration, the data control circuit conveys data of a first data width between a first integer number of the physical banks per read operation and the data terminals, and the plurality of physical banks collectively provide a first memory depth, and
in the second width configuration, the data control circuit conveys data of a second data width between a second integer number of the physical banks per read operation and the data terminals, the second data width wider than the first data width, the second integer number larger than the first integer number, and the plurality of physical banks collectively provide a second memory depth; and
wherein the memory device loads a first page of sense amplifiers in the first number of the physical banks for activate operation in the first width configuration and loads a second page of sense amplifiers in the second number of physical banks for activate operations in the second width configuration, the first page smaller than the second page.
2. The memory device of claim 1 , further comprising a wire-bonding option to receive the memory-width configuration value.
3. The memory device of claim 1 , further comprising a metal layer connection to receive the memory-width configuration value.
4. The memory device of claim 1 , wherein the physical banks further comprise a row decoder, and wherein the data control circuit minimizes row-access power in the first width configuration by limiting row accesses to the first integer number of the physical banks.
5. The memory device of claim 1 , wherein the second integer is at least two, each physical bank is of a physical-bank width, and wherein the data control circuit combines the second integer number of physical banks into a logical bank of the second data width.
6. The memory device of claim 5 , wherein the logical bank consists of four of the physical banks.
7. The memory device of claim 1 , wherein the data control circuit supports exactly three width configurations, including the first and second width configurations and a third width configuration, wherein in the third width configuration, the data control circuit conveys data of a third data width, wider than the second data width, between a third integer number of the physical banks and the data terminals.
8. The memory device of claim 7 , wherein the second data width is twice the first data width, and the third data width is twice the second data width.
9. The memory device of claim 1 , further comprising latches disposed between the data control circuit and the data terminals.
10. The memory device of claim 1 , further comprising data buffers disposed between the data control circuit and the data terminals.
11. The memory device of claim 1 , wherein the data control circuit comprises a crossbar switch.
12. The memory device of claim 1 , further comprising an address buffer, to store memory addresses, connected to the data control circuit.
13. The memory device of claim 12 , wherein the data control circuit selects between groups of the physical banks responsive to a bit of the memory addresses.
14. The memory device of claim 13 , wherein the groups are of the first integer number in the first width configuration and are of the second integer number in the second width configuration.
15. The memory device of claim 1 , embodied as a dynamic random access memory device.
16. A memory module comprising:
a printed-circuit board supporting conductive traces and including module pins; and
memory devices disposed on the printed-circuit board and having data pins connected to the module pins via the conductive traces, each memory device including:
an input to receive memory-width configuration value;
a plurality of physical banks, each physical bank including columns of memory cells coupled to corresponding sense amplifiers; and
a data control circuit coupling the physical banks with the data pins, the data control circuit supporting first and second width configurations responsive to the configuration value;
wherein, for each memory device:
in the first width configuration, the data control circuit conveys data of a first data width between a first integer number of the physical banks per read operation and the data pins, and the plurality of physical banks collectively provide a first memory depth, and
in the second width configuration, the data control circuit conveys data of a second data width between a second integer number of the physical banks and the data pins, the second data width wider than the first data width, the second integer number larger than the first integer number, and the plurality of physical banks collectively provide a second memory depth; and
wherein the memory device loads a first page of sense amplifiers in the first number of the physical banks for activate operations in the first width configuration and loads a second page of the sense amplifiers in the second number of physical banks for activate operations in the second width configuration, the first page smaller than the second page.
17. The memory module of claim 16 , further comprising a wire-bonding option to receive the memory-width configuration value.
18. The memory module of claim 16 , wherein the physical banks further comprise a row decoder, and wherein the data control circuit minimizes row-access power in the first width configuration by limiting row accesses to the first integer number of the physical banks.
19. The memory module of claim 16 , wherein the second integer is at least two, each physical bank is of a physical-bank width, and wherein the data control circuit combines the second integer number of physical banks into a logical bank of the second data width.
20. The memory module of claim 19 , wherein the logical bank consists of four of the physical banks.