Nonvolatile semiconductor memory device and method of manufacturing the same
According to one embodiment, a nonvolatile semiconductor memory device includes a memory cell and a select gate transistor formed on a semiconductor substrate. The memory cell includes a first gate insulating film, a first charge storage layer, a first intergate insulating film, and a first control gate. The first gate insulating film, the first charge storage layer, the first intergate insulating film, and the first control gate are formed on the semiconductor substrate in order. The select gate transistor includes a second gate insulating film, a first gate electrode, a second intergate insulating film, and a second control gate. The second gate insulating film, the first gate electrode, the second intergate insulating film, and the second control gate are formed on the semiconductor substrate in order. The second intergate insulating film different first and second thicknesses.
1. A nonvolatile semiconductor memory device comprising:
a memory cell formed on a semiconductor substrate, the memory cell comprising
a first gate insulating film formed on the semiconductor substrate,
a first charge storage layer formed on the first gate insulating film,
a first intergate insulating film formed on the first charge storage layer, and
a first control gate formed on the first intergate insulating film; and
a select gate transistor formed on the semiconductor substrate, the select gate transistor comprising
a second gate insulating film formed on the semiconductor substrate,
a first gate electrode formed on the second gate insulating film,
a second intergate insulating film formed on the first gate electrode and having different first and second thicknesses, and
a second control gate formed on the second intergate insulating film.
2. The device according to claim 1 , wherein
the first thickness is the same as the thickness of the first intergate insulating film, and the second thickness is smaller than the first thickness.
3. The device according to claim 1 , wherein
the first gate electrode has the same thickness as the first charge storage layer.
4. The device according to claim 1 , wherein
the second intergate insulating film comprises stacked first and second films, the total thickness of the stacked first and second films comprises the first thickness, and the first film has the second thickness.
5. The device according to claim 4 , wherein
the first film comprises a first insulating film disposed on the first gate electrode, and the second film comprises second and third insulating films disposed on the first insulating film.
6. The device according to claim 5 , wherein
the first insulating film comprises a silicon nitride film, and the second and third insulating films comprise oxide films.
7. The device according to claim 4 , wherein
the first film comprises first and second insulating films disposed on the first gate electrode in order, and the second film comprises third and fourth insulating films disposed on the second insulating film.
8. The device according to claim 7 , wherein
the second insulating film comprises a silicon nitride film, and the first, third, and fourth insulating films comprise oxide films.
9. The device according to claim 1 , further comprising:
a booster circuit which is connected to the select gate transistor and which generates a first voltage applied to the select gate transistor; and
a controller which steps up the first voltage applied to the second control gate of the select gate transistor in accordance with the electric connection between the first gate electrode and the second control gate of the select gate transistor.
10. The device according to claim 9 , wherein
the controller holds the first voltage applied to the second control gate of the select gate transistor to a voltage that does not cause the second gate insulating film to break down.
11. The device according to claim 1 , further comprising:
a booster circuit which is connected to the select gate transistor and which generates a first voltage applied to the select gate transistor; and
a controller which repeatedly applies the first voltage to the second control gate of the select gate transistor in accordance with the electric connection between the first gate electrode and the second control gate of the select gate transistor.
12. The device according to claim 1 , further comprising:
a controller which changes the voltage of a bit line connected to the select gate transistor in accordance with the electric connection between the first gate electrode and the second control gate of the select gate transistor.
13. The device according to claim 1 , wherein
a plurality of memory cells are connected in series, and the select gate transistors are disposed at both ends of the memory cells connected in series.