ADVANCED TRANSISTORS WITH PUNCH THROUGH SUPPRESSION
An advanced transistor with punch through suppression includes a gate with length Lg, a well doped to have a first concentration of a dopant, and a screening region positioned under the gate and having a second concentration of dopant. The second concentration of dopant may be greater than 5×10 18 dopant atoms per cm 3 . At least one punch through suppression region is disposed under the gate between the screening region and the well. The punch through suppression region has a third concentration of a dopant intermediate between the first concentration and the second concentration of dopant. A bias voltage may be applied to the well region to adjust a threshold voltage of the transistor.
1 . A field effect transistor structure, comprising:
a substrate;
a gate atop the substrate;
a source;
a drain;
a plurality of distinct doped regions in the substrate underlying the gate and extending between the source and the drain, the plurality of doped regions defining a dopant profile for the transistor, the dopant profile having a peak dopant concentration at a first depth from the gate and an intermediate dopant concentration at a second depth from the gate, the intermediate dopant concentration establishing a first notch in the dopant profile; and
an epitaxially grown substantially undoped channel underlying the gate and overlying the plurality of doped regions.
2 . The transistor of claim 1 , wherein the first depth is deeper below the gate than the second depth.
3 . The transistor of claim 1 , wherein the first depth is shallower below the gate than the second depth.
4 . The transistor of claim 1 , wherein the first depth is approximately one half of a length of the gate.
5 . The transistor of claim 1 , wherein the dopant profile includes a second intermediate dopant concentration at a third depth from the gate, the second intermediate dopant concentration establishing a second notch in the dopant profile.
6 . The transistor of claim 1 , wherein the first depth sets a depletion depth for the transistor when a voltage is applied to the gate.
7 . The transistor of claim 1 , wherein the dopant concentration at the second depth is associated with a threshold voltage of the transistor.
8 . The transistor of claim 1 , further comprising:
a bias structure coupled to the source, the bias structure operable to modify an operational threshold voltage of the transistor.
9 . The transistor of claim 8 , further comprising:
a fixed voltage source coupled to the bias structure to statically set the threshold voltage of the transistor.
10 . The transistor of claim 8 , further comprising:
a variable voltage source coupled to the bias structure to dynamically adjust the threshold voltage of the transistor.
11 . A die, comprising:
a substrate;
a plurality of field effect transistor structures supported by the substrate each having a gate, a source, and a drain;
wherein at least one of the transistors has a plurality of doped regions in the substrate underlying the gate and extending between the source and drain, the plurality of doped regions defining a dopant profile for the transistor, the dopant profile having a peak dopant concentration at a first depth from the gate and an intermediate dopant concentration at a second depth from the gate, the intermediate dopant concentration establishing a first notch in the dopant profile;
wherein each of the plurality of transistors include a channel commonly formed by an undoped blanket epitaxial growth.
12 . The transistor of claim 11 , wherein the dopant profile includes a second intermediate dopant concentration at a third depth from the gate, the second intermediate dopant concentration establishing a second notch in the dopant profile.
13 . The transistor of claim 11 , wherein the peak dopant concentration at the first depth sets a depletion depth for the transistor.
14 . The transistor of claim 11 , wherein the dopant concentration at the second depth is associated with a threshold voltage of the transistor.
15 . The die of claim 11 , further comprising:
a bias structure coupled to the source of at least one transistor, the bias structure operable to modify an operational threshold voltage of the transistor.
16 . The die of claim 15 , further comprising:
a fixed voltage source coupled to the bias structure to statically set the threshold voltage of the transistor.
17 . The die of claim 15 , further comprising:
a variable voltage source coupled to the bias structure to dynamically adjust the threshold voltage of the transistor.
18 . The die of claim 15 , wherein the plurality of transistors are separated into different bias sections, a first bias section providing no threshold voltage adjustment, a second bias section operable to provide static threshold voltage adjustment, and a third bias section operable to provide dynamic threshold voltage adjustment.
19 . The die of claim 18 , wherein any of the bias sections includes transistors with different threshold voltages with or without any adjustment.