Discrete three-dimensional memory comprising off-die address/data translator
The present invention discloses a discrete three-dimensional memory (3D-M). Its 3D-M arrays are located on at least one 3D-array die, while its address-data translator (A/D-translator) is located on a separate peripheral-circuit die. The A/D-translator converts at least an address and/or data between logical space and physical space for the 3D-array die. A single A/D-translator die can support multiple 3D-array dies.
1. A discrete three-dimensional memory (3D-M), comprising:
a first 3D-array die comprising at least a first 3D-M array including a plurality of vertically stacked memory cells;
a first peripheral-circuit die comprising an address/data translator for converting at least an address and/or data between logical space and physical space for said first 3D-array die;
a second peripheral-circuit die comprising a read/write-voltage generator for providing said first 3D-array die with at least a read voltage and/or a write voltage other than the voltage supply;
wherein said first 3D-array die, said first peripheral-circuit die and said second peripheral-circuit die are separate dies.
2. The memory according to claim 1 , further comprising a second 3D-array die comprising at least a second 3D-M array including a plurality of vertically stacked memory cells, wherein:
said address/data translator converts at least an address and/or data between logical space and physical space for said second 3D-array die;
said read/write-voltage generator provides said second 3D-array die with at least a read voltage and/or a write voltage other than the voltage supply;
said first 3D-array die, said second 3D-array die, said first peripheral-circuit die and said second peripheral-circuit die are separate dies.
3. The memory according to claim 1 , wherein said 3D-M comprises a three-dimensional read-only memory (3D-ROM) or a three-dimensional random-access memory (3D-RAM).
4. The memory according to claim 1 , wherein said 3D-M comprises a three-dimensional mask-programmed read-only memory (3D-MPROM) or a three-dimensional electrically-programmable read-only memory (3D-EPROM).
5. The memory according to claim 1 , wherein said 3D-M comprises at least one of a memristor, a resistive random-access memory (RRAM or ReRAM), a phase-change memory, a programmable metallization cell (PMC), and a conductive-bridging random-access memory (CBRAM).
6. The memory according to claim 1 , wherein said address/data translator comprises at least one of an address mapping table, a faulty block table and a wear management table.
7. The memory according to claim 1 , wherein said address/data translator comprises at least one of an ECC-encoder and an ECC-decoder.
8. The memory according to claim 1 , wherein said 3D-array and peripheral-circuit dies are located in a memory package, a memory module, a memory card or a solid-state drive.
9. The memory according to claim 1 , wherein said first peripheral-circuit die comprises fewer back-end layers than said first 3D-array die.
10. The memory according to claim 1 , wherein said first peripheral-circuit die comprises different interconnect materials than said first 3D-array die.
11. The memory according to claim 1 , wherein said first peripheral-circuit die comprises more substrate interconnect layers than said first 3D-array die.
12. The memory according to claim 1 , wherein said second peripheral-circuit die comprises fewer back-end layers than said first 3D-array die.
13. The memory according to claim 1 , wherein said second peripheral-circuit die comprises different interconnect materials than said first 3D-array die.
14. The memory according to claim 1 , wherein said second peripheral-circuit die comprises more substrate interconnect layers than said first 3D-array die.
15. The memory according to claim 2 , wherein said first peripheral-circuit die comprises fewer back-end layers than said second 3D-array die.
16. The memory according to claim 2 , wherein said first peripheral-circuit die comprises different interconnect materials than said second 3D-array die.
17. The memory according to claim 2 , wherein said first peripheral-circuit die comprises more substrate interconnect layers than said second 3D-array die.
18. The memory according to claim 2 , wherein said second peripheral-circuit die comprises fewer back-end layers than said second 3D-array die.
19. The memory according to claim 2 , wherein said second peripheral-circuit die comprises different interconnect materials than said second 3D-array die.
20. The memory according to claim 2 , wherein said second peripheral-circuit die comprises more substrate interconnect layers than said second 3D-array die.