High voltage LED with improved heat dissipation and light extraction

1. A lighting apparatus, comprising:

a polygon die including a plurality of light-emitting diodes (LEDs), and wherein each LED includes:

a plurality of epi-layers, the epi-layers containing a p-type layer, an n-type layer, and a multiple quantum well (MQW) disposed between the p-type layer and the n-type layer; and

a p-type electrode and an n-type electrode electrically coupled to the p-type layer and the n-type layer, respectively; and

a submount to which each of the LEDs is coupled, wherein the p-type and the n-type electrodes are located between the submount and the epi-layers, wherein the submount contains a plurality of conductive elements configured to electrically couple at least a portion of the plurality of LEDs in series, and wherein at least some of the plurality of LEDs have non-rectangular top view shapes.

2. The lighting apparatus of claim 1 , wherein at least some of the LEDs have different top view shapes than a rest of the LEDs.

3. The lighting apparatus of claim 1 , wherein at least some of the LEDs have non-rectangular polygonal top view shapes.

4. The lighting apparatus of claim 1 , wherein at least some of the LEDs have some curved sides in a top view.

5. The lighting apparatus of claim 1 , wherein a first distance separating a first subset of adjacent LEDs is greater than a second distance separating a second subset of adjacent LEDs.

6. The lighting apparatus of claim 1 , wherein the lighting apparatus includes a plurality of polygon dies.

7. The lighting apparatus of claim 1 , wherein the submount includes a metal material, a silicon-on-insulator, a silicon submount, a ceramic submount, or a metal core printed circuit board (MCPCB) submount.

8. The lighting apparatus of claim 7 , wherein at least some of the conductive elements include: metal lines of an interconnect layer formed over the silicon submount, or metal traces formed over the MCPCB submount.

9. The lighting apparatus of claim 1 , wherein the plurality of LEDs include an X number of LEDs, wherein the number X is selected so that the X number of LEDs, when electrically coupled together in series, has a maximum operational voltage greater than about 170 volts.

10. A lighting apparatus, comprising:

a die including a plurality of light-emitting diodes (LEDs), and wherein each LED includes:

a plurality of epi-layers, the epi-layers containing a p-doped III-V compound layer, an n-doped III-V compound layer, and a multiple quantum well (MQW) disposed between the p-doped III-V compound layer and the n-doped III-V compound layer; and

a first electrode and a second electrode electrically coupled to the p-doped III-V compound layer and the n-doped III-V compound layer, respectively; and

a submount bonded to the die,

wherein the first and second electrodes are located between the submount and the epi-layers; and

wherein at least one of the following is true:

some of the LEDs have different patterns than other LEDs in a top view;

some of the LEDs have non-rectangular polygonal patterns in a top view; and

some of the LEDs have one or more curved edges in a top view.

11. The lighting apparatus of claim 10 , wherein the submount contains a plurality of conductive elements configured to electrically couple together at least a subset of the plurality of LEDs in series.

12. The lighting apparatus of claim 10 , wherein the lighting apparatus includes a plurality of polygonal dies, said die being one of the polygonal dies.

13. The lighting apparatus of claim 10 , wherein the submount includes a metal material, a silicon-on-insulator, a silicon submount, a ceramic submount, or a metal core printed circuit board (MCPCB) submount.

14. The lighting apparatus of claim 13 , wherein at least some of the conductive elements include: metal lines of an interconnect layer formed over the silicon submount, or metal traces formed over the MCPCB submount.

15. A method of fabricating a high voltage light-emitting diode apparatus, the method comprising:

growing a plurality of epi-layers over a growth substrate in one or more epitaxial processes, wherein the plurality of epi-layers include a p-doped III-V compound layer, an n-doped III-V compound layer, and a multiple quantum well (MQW) disposed between the p-doped III-V compound layer and the n-doped III-V compound layer;

removing a portion of the epi-layers over the growth substrate to form streets for forming a plurality of separated light-emitting diodes (LEDs) by etching according to a lithography pattern, said pattern including non-rectangle and each LED comprising the p-doped III-V compound layer, the n-doped III-V compound layer, and the multiple quantum well (MQW);

forming a p-type electrode and an n-type electrode over each of the LEDs, wherein the p-type electrode is electrically coupled to the p-doped III-V compound layer, and the n-type electrode is electrically coupled to the n-doped III-V compound layer;

bonding the LEDs to a submount so that the p-type and the n-type electrodes are located between the submount and the epi-layers after the bonding; and

thereafter thinning or removing the growth substrate.

16. The method of claim 15 , wherein the removing is performed so that at least one of the following is true:

at least some of the LEDs have different shapes than a rest of the LEDs in a top view;

at least some of the LEDs have non-rectangular polygonal shapes in a top view; and

at least some of the LEDs have one or more curved sides in a top view.

17. The method of claim 15 , wherein:

the growth substrate includes a sapphire material;

the submount includes one of: a metal material, a silicon-on-insulator, a silicon submount, a ceramic submount, and a metal core printed circuit board (MCPCB) submount;

the submount contains a plurality of conductive elements; and

the bonding step is performed so that at least a subset of the LEDs are electrically coupled in series by the conductive elements.

18. The method of claim 15 , wherein the plurality of separated LEDs are parts of a polygonal die.

19. The method of claim 15 , wherein the bonding step comprises a wafer level bonding process.

20. The method of claim 15 , wherein the bonding step comprises a die level bonding process.