Electromagnetic interference reduction in wireline applications using differential signal compensation

1. An integrated circuit device comprising:

a differential driver to generate a differential signal, the differential signal comprising true and complement signal components that exhibit a relative timing relationship;

a transmission port for delivering the differential signal to a transmission medium;

a common mode detection circuit for detecting a common mode signal associated with the differential signal;

control circuitry to generate a control signal based on the detected common mode signal; and

timing circuitry to adjust the relative timing between the true and the complement signal components based on the control signal.

2. The integrated circuit according to claim 1 wherein:

the differential driver comprises a voltage-mode pseudo-differential driver.

3. The integrated circuit according to claim 1 wherein the common mode detection circuit includes:

first and second impedance circuits having matched impedance values and respectively coupled to the transmission port, the impedance circuits joined at a detection node to form an impedance divider;

wherein the detection node provides a detected waveform indicative of a common-mode exhibited at the transmission port.

4. The integrated circuit according to claim 3 wherein the common mode detection circuit further includes:

a gain amplifier having an input coupled to the detection node and an output to generate an amplified version of the detected waveform; and

an accumulator circuit to receive the detected waveform and generate an accumulation signal, the control signal based on a comparison between the accumulation signal and a predetermined threshold value.

5. The integrated circuit according to claim 4 wherein:

the accumulator circuit comprises an analog integrator.

6. The integrated circuit according to claim 4 wherein:

the accumulator circuit comprises a digital counter.

7. The integrated circuit according to claim 1 :

wherein the true signal component is clocked by a first timing reference, and the complement signal component is clocked by a second timing reference; and

wherein the timing circuitry includes an adjustable delay circuit to adjust a timing of one or more of the timing references in response to the control signal.

8. The integrated circuit of claim 1 :

wherein the timing circuitry includes an adjustable delay circuit to delay differential signal rise or fall transition times with respect to the other signal component.

9. The integrated circuit of claim 1 wherein the common mode detection circuit is coupled to the transmission port.

10. The integrated circuit of claim 1 wherein the common mode detection circuit comprises:

a replica driver having electrical characteristics that substantially match electrical characteristics exhibited by the differential driver;

first and second impedance circuits having matched impedance values and respectively coupled to the replica driver, the impedance circuits joined at a detection node to form an impedance divider;

a gain amplifier having an input coupled to the detection node and an output to generate an amplified version of the detected waveform; and

an accumulator circuit to receive the detected waveform and generate an accumulation signal, the control signal based on a comparison between the accumulation signal and a predetermined threshold value.

11. A method of reducing radio frequency interference (RFI) emitted by a differential driver, the method comprising:

generating a differential signal having a true signal component and a complement signal component, the differential signal for transmission along a transmission medium;

detecting a level of common mode associated with the generated differential signal prior to transmission on the medium and generating a signal indicative of the detected level;

accumulating the detected common mode signal with previously detected common mode signals to generate a running accumulation value;

comparing the running accumulation value to a predetermined threshold; and

adjusting a relative timing between the true signal component and the complement signal component if the predetermined threshold is exceeded.

12. The method according to claim 11 wherein the detecting, accumulating, comparing and adjusting are carried out by circuitry formed on a common integrated circuit chip.

13. The method of claim 11 wherein the detecting comprises:

sensing the differential signal and generating a signal representative of the common mode through an impedance network;

amplifying the signal representative of the common mode;

accumulating the signal representative of the common mode with prior detected signals to generate an accumulation value; and

generating a control signal if the accumulation value exceeds a predetermined threshold.

14. The method according to claim 11 , wherein the true and complement signal components are responsive to respective clock signals, and the adjusting a relative timing between the true and complement signals comprises:

delaying one or both of the respective clock signals.

15. The method according to claim 11 wherein accumulating comprises integrating the signal representative of the common mode.

16. The method according to claim 11 wherein accumulating comprises incrementing a count based on detections of the signal representative of the common mode.

17. The method of claim 11 wherein the detecting comprises:

generating a replica differential signal that exhibits electrical parameters that substantially track electrical parameters associated with the differential signal;

sensing the replica differential signal and detecting a signal representative of the common mode through an impedance network;

amplifying the signal representative of the common mode;

accumulating the signal representative of the common mode with prior detected signals to generate an accumulation value;

generating a control signal if the accumulation value exceeds a predetermined threshold; and

adjusting the relative timing based on the common mode signal detected from the generation of the replica differential signal.

18. The method according to claim 17 wherein accumulating comprises integrating the signal representative of the common mode.

19. The method according to claim 17 wherein accumulating comprises incrementing a count based on detections of the signal representative of the common mode.

20. A differential driver circuit formed on an integrated circuit chip, the differential driver circuit comprising:

a voltage-mode differential driver to generate a differential signal, the differential signal comprising true and complement signal components that exhibit a relative timing relationship;

respective true and complement signal pins for delivering the true and complement signal components to a transmission medium;

a common mode detection circuit coupled to the true and complement signal pins for detecting a common mode signal associated with a timing imbalance between the true and complementary signal components, the common mode detection circuit including

a replica driver having electrical characteristics that substantially match electrical characteristics exhibited by the differential driver;

first and second impedance circuits having matched impedance values and respectively coupled to the replica driver, the impedance circuits joined at a detection node to form an impedance divider;

a gain amplifier having an input coupled to the detection node and an output to generate an amplified version of the detected waveform; and

an accumulator circuit to receive the detected waveform and generate an accumulation signal, the control signal based on a comparison between the accumulation signal and a predetermined threshold value; and

timing circuitry to adjust the relative timing relationship between the true and the complement signal components based on the control signal.