Transistors and methods of manufacturing the same
Transistors, and methods of manufacturing the transistors, include graphene and a material converted from graphene. The transistor may include a channel layer including graphene and a gate insulating layer including a material converted from graphene. The material converted from the graphene may be fluorinated graphene. The channel layer may include a patterned graphene region. The patterned graphene region may be defined by a region converted from graphene. A gate of the transistor may include graphene.
1. A transistor, comprising:
a channel layer including graphene;
a gate insulating layer on a surface of the channel layer, the gate insulating layer including fluorinated graphene;
a gate facing the channel layer, the gate insulating layer being between the gate and the channel layer; and
a source and a drain electrically connected to first and second regions of the channel layer, respectively.
2. The transistor of claim 1 , wherein the gate includes graphene.
3. The transistor of claim 1 , wherein,
the channel layer includes a patterned graphene region, and
the patterned graphene region is a nanoscale patterned region.
4. The transistor of claim 3 , wherein,
the channel layer includes a fluorinated graphene region and a non-fluorinated graphene region, and
the non-fluorinated graphene region corresponds to the patterned graphene region.
5. The transistor of claim 3 , wherein the patterned graphene region includes a graphene nanoribbon (GNR) region.
6. The transistor of claim 3 , wherein the patterned graphene region includes a graphene nanomesh (GNM) region.
7. The transistor of claim 1 , wherein the channel layer is a single-layer graphene.
8. The transistor of claim 1 , wherein the gate insulating layer is a fluorinated single-layer graphene.
9. The transistor of claim 1 , wherein the gate insulating layer further comprises an insulating layer between the fluorinated graphene and the gate.
10. The transistor of claim 1 , wherein,
the gate insulating layer is on a portion of the channel layer,
the source is on the channel layer at one side of the gate insulating layer, and
the drain is on the channel layer at another side of the gate insulating layer.
11. The transistor of claim 10 , further comprising:
a first graphene region between the channel layer and the source; and
a second graphene region between the channel layer and the drain.
12. A transistor, comprising:
a channel layer including a region comprised of graphene with a chemical modifier attached and a patterned graphene region defined by the region;
a gate insulating layer on a surface of the channel layer, the gate insulating layer including fluorinated graphene;
a gate facing the channel layer, the gate insulating layer being between the gate and the channel layer; and
a source and a drain electrically connected to first and second regions of the channel layer, respectively.
13. The transistor of claim 12 , wherein the region comprised of graphene with a chemical modifier attached is chemically converted from graphene without the chemical modifier attached.
14. The transistor of claim 12 , wherein the region comprised of graphene with a chemical modifier attached is a fluorinated graphene region.
15. The transistor of claim 12 , wherein the patterned graphene region includes a graphene nanoribbon (GNR) region or a graphene nanomesh (GNM) region.
16. The transistor of claim 12 , wherein the gate includes graphene.
17. A transistor, comprising:
a channel layer, a gate insulating layer, a gate, a source, and a drain,
wherein the channel layer, the gate insulating layer, and the gate include at least one of graphene and a material comprised of graphene with a chemical modifier attached.
18. The transistor of claim 17 , wherein the material comprised of graphene with a chemical modifier attached is chemically converted from graphene without a chemical modifier attached.
19. The transistor of claim 17 , wherein the gate insulating layer includes fluorinated graphene.
20. The transistor of claim 17 , wherein the channel layer includes graphene.
21. The transistor of claim 20 , wherein the channel layer includes a fluorinated graphene region and a patterned graphene region defined by the fluorinated graphene region.
22. The transistor of claim 17 , wherein the gate includes graphene.