Semiconductor device PN junction fabrication using optical processing of amorphous semiconductor material

1. A method for fabricating an electrical device having a P-N junction, the method comprising:

depositing a layer of amorphous semiconductor material onto a crystalline semiconductor base, wherein the crystalline semiconductor base comprises a crystalline phase of a same semiconductor as the amorphous layer; and

growing the layer of amorphous semiconductor material into a layer of crystalline semiconductor material that is epitaxially matched to a lattice structure of the crystalline semiconductor base by applying an optical energy that penetrates through at least the amorphous semiconductor material;

wherein the optical energy is controlled to penetrate the amorphous semiconductor material such as to produce uniform heating across an interfacing surface between the amorphous semiconductor material and the crystalline semiconductor base;

wherein the optical energy is applied in a single application to produce the uniform heating across the interfacing surface for a duration lasting until the amorphous semiconductor material is completely crystallized.

2. The method of claim 1 , wherein an intensity profile of the optical energy is controlled to produce the uniform heating.

3. The method of claim 1 , wherein the amorphous semiconductor material is amorphous silicon (a-Si) and the crystalline semiconductor base comprises a mono-crystalline silicon (c-Si).

4. The method of claim 1 , wherein the crystalline semiconductor base comprises a multi-crystalline structure.

5. The method of claim 1 , wherein the amorphous semiconductor material is an n-type semiconductor material and the crystalline semiconductor base comprises a p-type semiconductor material.

6. The method of claim 1 , wherein depositing a layer of amorphous semiconductor material comprises at least one of, electron beam deposition, Plasma-enhanced chemical vapor deposition (PECVD), sputtering, or hot-wire chemical vapor deposition (HWCVD).

7. The method of claim 1 , wherein the optical energy is provided by separately controlled regions of light sources, each region having its own prescribed intensity profile.

8. The method of claim 7 , wherein the optical energy is controlled to produce the uniform heating by independently varying optical energy delivered by each region of light sources.

9. The method of claim 1 , wherein the amorphous semiconductor material and the crystalline semiconductor base are conveyed through an optical furnace during application of the optical energy.

10. The method of claim 1 , further comprising:

applying an anti-reflective coating after the amorphous semiconductor material is completely crystallized.

11. The method of claim 1 , further comprising:

applying one or both of passivation layers and electrically conductive layers.

12. The method of claim 1 , wherein the crystalline semiconductor base comprises one or more back layers.

13. The method of claim 12 , wherein the one or more back layers comprise at least one aluminum (Al) back layer or at least one boron P+ back layer.

14. A method for fabricating an electrical device having a P-N junction, the method comprising:

placing a semiconductor wafer into an optical cavity furnace, wherein the semiconductor wafer comprises a layer of amorphous semiconductor material deposited onto a crystalline semiconductor base, and wherein the optical cavity furnace comprises:

a chamber configured to accept the semiconductor wafer; and

a plurality of light sources configured to apply optical energy into the chamber and onto the semiconductor wafer;

operating the plurality of light sources to generate an optical energy profile incident onto the amorphous semiconductor material that produces uniform heating across an interfacing surface within the semiconductor wafer between the amorphous semiconductor material and the crystalline semiconductor base; and

growing the layer of amorphous semiconductor material from the uniform heating at the interfacing surface into a layer of crystalline semiconductor material that is epitaxially matched to the lattice structure of the crystalline semiconductor base;

wherein the optical energy is controlled to penetrate at least the amorphous semiconductor material such as to produce the uniform heating; and

wherein the optical energy is applied in a single application to produce the uniform heating across the interfacing surface for a duration lasting until the amorphous semiconductor material is completely crystallized.

15. The method of claim 14 , wherein the amorphous semiconductor material is amorphous silicon (a-Si) and the crystalline semiconductor base comprises a mono-crystalline silicon (c-Si).

16. The method of claim 14 , wherein the crystalline semiconductor base comprises a multi-crystalline structure.

17. The method of claim 14 , wherein the amorphous semiconductor material is an n-type semiconductor material and the crystalline semiconductor base comprises a p-type semiconductor material.

18. The method of claim 14 , further comprising

depositing the layer of amorphous semiconductor material onto the crystalline semiconductor base.

19. The method of claim 14 , wherein the optical energy is applied to the semiconductor wafer at least until the amorphous semiconductor material is completely transformed into the layer of crystalline semiconductor material.

20. The method of claim 14 , wherein the optical energy is controlled to produce the uniform heating along the interfacing surface within the semiconductor wafer by independently varying optical energy delivered by respective segments of the plurality of light sources.

21. The method of claim 14 , wherein the semiconductor wafer is placed on a carrier and conveyed through the optical cavity furnace during the application of the optical energy.

22. The method of claim 14 , further comprising:

applying an anti-reflective coating after the layer of amorphous semiconductor material is completely crystallized; and

applying one or both of passivation layers and electrically conductive layers to the semiconductor wafer.

23. The method of claim 14 , wherein the crystalline semiconductor base comprises one or more back layers.

24. The method of claim 23 , wherein the one or more back layers comprise at least one aluminum (Al) back layer or at least one boron P+ back layer.