Trench FET with ruggedness enhancement regions
View Patent ↗According to an exemplary implementation, a field-effect transistor (FET) includes first and second gate trenches extending to a drift region of a first conductivity type. The FET also includes a base region of a second conductivity type that is situated between the first and second gate trenches. A ruggedness enhancement region is situated between the first and second gate trenches, where the ruggedness enhancement region is configured to provide an enhanced avalanche current path from a drain region to the base region when the FET is in an avalanche condition. The enhanced avalanche current path is away from the first and second gate trenches. The ruggedness enhancement region can be of the second conductivity type that includes a higher dopant concentration than the base region. Furthermore, the ruggedness enhancement region can be extending below the first and second gate trenches.
1. A field-effect transistor (FET) comprising:
first and second gate trenches having respective trench bottoms extending to a drift region of a first conductivity type;
a base region of a second conductivity type that is situated between said first and second gate trenches;
a plurality of ruggedness enhancement regions situated between said first and second gate trenches;
a contact region, of said second conductivity type, that is situated over said base region and under a contact opening, wherein a maximum width of each of said plurality of ruggedness enhancement regions is substantially less than a maximum width of said contact region;
wherein said base region extends as a stripe, and said plurality of ruggedness enhancement regions are dispersed below said stripe;
wherein said ruggedness enhancement regions have a highest dopant concentration at least partially above said respective trench bottoms;
wherein said ruggedness enhancement regions are of said second conductivity type having a higher dopant concentration than said base region, and wherein said contact region is of said second conductivity type having a higher dopant concentration than said ruggedness enhancement regions.
2. The FET of claim 1 , wherein said ruggedness enhancement regions extend below said first and second gate trenches.
3. The FET of claim 1 , wherein said ruggedness enhancement regions extend as respective stripes along said base region.
4. The FET of claim 1 , wherein groups of said ruggedness enhancement regions are aligned substantially perpendicular to said stripe.
5. The FET of claim 1 , wherein said plurality of ruggedness enhancement regions directly adjoin said base region and extend from said base region into said drift region.
6. The FET of claim 1 , further comprising spacers formed on sidewalls of said contact opening.