System and method for memory access in server communications
A random access memory includes a plurality of memories configured to store and provide data, and a test module coupled to the plurality of memories, wherein the test module is configured to write a first write data pattern into at last a first portion of the plurality of memories in response to a data pattern value, wherein the test module is configured to read a read data pattern from the plurality of memories, wherein the test module is configured to compare the first write data pattern to the read data pattern, and wherein the test module is configured to report errors in response to a comparison of the write data pattern to the read data pattern.
1. A memory module comprising:
a circuit board comprising a plurality of contacts, wherein the plurality of contacts are configured to be coupled to an external processor, and configured to receive storage data and register data from the external processor;
a register module coupled to a first plurality of contacts on the circuit board, wherein the register module is configured to store the register data; and
a plurality of DRAMs coupled to a second plurality of contacts on the circuit board and coupled to the register module, wherein a DRAM of the plurality of DRAMs includes a plurality of memories and a test module;
wherein the test module is configured to write a first write data pattern into at least a first portion of the plurality of memories in response to a data pattern value selected from a group consisting: a total error count, an overflow flag;
wherein the test module is configured to read a read data pattern from the plurality of memories;
wherein the test module is configured to compare the first write data pattern to the read data pattern;
wherein the test module is configured to report errors in response to a comparison of the write data pattern to the read data pattern.
2. The memory module of claim 1 further comprising:
an externally-addressable spare column; and
wherein the register module is configured to use the externally-addressable spare column in response to the comparison.
3. The memory module of claim 1
wherein the DRAM includes a buffer; and
wherein the test module is configured to store results of the comparison of the write data pattern to the read data pattern into the buffer.
4. The memory module of claim 1
wherein the test module is configured to determine the first write data pattern from a plurality of write data patterns, in response to the register data.
5. The memory module of claim 1 wherein the test module is configured to write the first write data pattern into the plurality of memories.
6. The memory module of claim 1 wherein the test module is also configured to write a second write data pattern into at least a second portion of the plurality of memories.
7. The memory module of claim 1 wherein the data pattern value comprises 1 to 3 bits of data.
8. The memory module of claim 1 wherein the test module is configured to report the errors to the external processor when the comparison is completed.
9. The memory module of claim 1 wherein the test module is configured to report the errors by being configured to modify a value of a register in the register module when the comparison is completed.
10. A random access memory comprises:
a plurality of memories configured to store and provide data; and
a test module coupled to the plurality of memories, wherein the test module is configured to write a first write data pattern into at least a first portion of the plurality of memories in response to a data pattern value selected from a group consisting: a total error count, an overflow flag, wherein the test module is configured to read a read data pattern from the plurality of memories, wherein the test module is configured to compare the first write data pattern to the read data pattern, and wherein the test module is configured to report errors in response to a comparison of the write data pattern to the read data pattern.
11. The random access memory of claim 10
wherein the DRAM further includes a buffer configured to store results of the comparison of the write data pattern to the read data pattern.
12. The random access memory of claim 10
wherein the test module is configured to determine the first write data pattern from a plurality of write data patterns, in response to external register data.
13. The random access memory of claim 10 wherein the test module is configured to write the first write data pattern into the plurality of memories.
14. The random access memory of claim 10 wherein the test module is also configured to write a second write data pattern into at least a second portion of the plurality of memories.
15. The random access memory of claim 10 wherein the test module is configured to provide up to eight different pre-determined data patterns.
16. The random access memory of claim 10 wherein the test module is configured to report the errors to an external processor when the comparison is completed.
17. The random access memory of claim 10 wherein the test module is configured report the errors by being configured to modify a value of a register in an external register module when the comparison is completed.
18. The random access memory of claim 10 wherein the test module is configured report the errors by being configured to modify a value of a register in an external register module during the comparison.