Method of manufacture for a semiconductor device

1. A method of manufacturing a semiconductor device, the method comprising:

providing a semiconductor layer of a first conductivity type;

forming a semiconductor layer of a second conductivity type on the semiconductor layer of the first conductivity type;

forming one or more insulator layers on the semiconductor layer of the second conductivity type;

etching a plurality of trenches in the semiconductor layer of the second conductivity type, thereby forming a portion of a plurality of CC trenches and a CG trench;

forming an oxide layer in the plurality of trenches and on the semiconductor layer of the second conductivity type;

forming a masking layer on a portion of the one or more insulating layers;

forming a gate oxide layer in the CG trench;

forming polysilicon gate material in the CG trench; forming a second insulator layer, thereby filling a portion of the CC trenches;

forming a second material, thereby filling a second portion of the CC trenches;

forming a third insulator layer, thereby filling a remainder of the CC trenches; forming one or more device regions;

forming a source metal layer;

wherein the semiconductor layer of the second conductivity type comprises a multi-layer structure including an n-type material layer on the semiconductor layer of the first conductivity type and a p-type material layer on the n-type material layer;

wherein the second material comprises aluminum fluoride; and

wherein the second material further comprises an insulating layer.

2. The method of claim 1 wherein the semiconductor layer of the first conductivity type comprises an n+ silicon substrate doped with at least one of phosphorus, antimony, or arsenic.

3. The method of claim 1 further comprising: forming a second oxide layer over the polysilicon gate material; and patterning the second oxide layer.

4. The method of claim 1 further comprising performing an etching process to extend a depth of the plurality of CC trenches.

5. The method of claim 1 further comprising: not forming a second insulator layer; and continuing the deposition of the second material, thereby filling the remainder of the CC trenches.

6. The method of claim 1 wherein etching the plurality of trenches in the semiconductor layer of the second conductivity type is performed concurrently.

7. A method of manufacturing a semiconductor device, the method comprising:

providing a semiconductor layer of a first conductivity type;

forming a semiconductor layer of a second conductivity type on the semiconductor layer of the first conductivity type;

forming an insulator layer on the semiconductor layer of the second conductivity type;

etching a trench into at least the semiconductor layer of the second conductivity type;

forming a thermal oxide layer in the trench and on the semiconductor layer of the second conductivity type;

implanting ions into the thermal oxide layer;

forming a second insulator layer, thereby filling at least a portion of the trench;

removing the second insulator layer from a portion of the trench;

forming an oxide layer in the trench and on the epitaxial layer;

forming a material in the trench; forming one or more device regions;

forming a third insulating layer over the material; patterning the third insulating layer;

forming a source metal layer;

wherein the semiconductor layer of the second conductivity type comprises a multi-layer structure including an n-type material layer on the semiconductor layer of the first conductivity type and a p-type material layer on the n-type material layer;

wherein the ions comprise cesium ions; and

further comprising: capping the second insulator layer; and performing a thermal treatment to anneal the cesium ions.

8. The method of claim 7 wherein the semiconductor layer of the first conductivity type comprises an n+ doped substrate doped with at least one of phosphorus, antimony, or arsenic.

9. The method of claim 7 wherein the semiconductor layer of the second conductivity type comprises an n-type material layer on the semiconductor layer of the first conductivity type.

10. The method of claim 7 wherein the trench extends to the semiconductor layer of the first conductivity type.

11. The method of claim 7 wherein the ions comprise iodine, bromine, chromium, aluminum, or chlorine ions.

12. The method of claim 11 further comprising: capping the second insulator layer; and performing a thermal treatment to anneal the iodine, bromine, chromium, aluminum, or chlorine ions.

13. The method of claim 7 further comprising thinning the semiconductor layer of the first conductivity type; and forming a drain metal layer.

14. The method of claim 7 wherein the material comprises polysilicon.