IP Library Granted Patent US 9,525,034
Granted Patent B2
US 9,525,034 · App. 13/799,246 · Granted Dec 20, 2016

Semiconductor device and manufacturing method thereof

Inventors: Shunpei Yamazaki (Tokyo, JP); Jun Koyama (Kanagawa, JP); Hiroyuki Miyake (Kanagawa, JP); Kei Takahashi (Kanagawa, JP); Kouhei Toyotaka (Kanagawa, JP); Masashi Tsubuku (Kanagawa, JP); Kosei Noda (Kanagawa, JP); Hideaki Kuwabara (Kanagawa, JP)
Assignee: Semiconductor Energy Laboratory Co., Ltd.
H01L29/26H01L27/1225H01L29/7869
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Quick Facts
Patent No.
US 9,525,034
App. No.
13/799,246
Granted
Dec 20, 2016
Kind
B2
Abstract

An object is to reduce leakage current and parasitic capacitance of a transistor used for an LSI, a CPU, or a memory. A semiconductor integrated circuit such as an LSI, a CPU, or a memory is manufactured using a thin film transistor in which a channel formation region is formed using an oxide semiconductor which becomes an intrinsic or substantially intrinsic semiconductor by removing impurities which serve as electron donors (donors) from the oxide semiconductor and has larger energy gap than that of a silicon semiconductor. With use of a thin film transistor using a highly purified oxide semiconductor layer with sufficiently reduced hydrogen concentration, a semiconductor device with low power consumption due to leakage current can be realized.

Claims (58)

1. A semiconductor device comprising:

a substrate;

a first conductive layer over the substrate;

a first insulating layer over the first conductive layer; and

a thin film transistor,

wherein the thin film transistor comprises:

a first gate electrode layer;

a first gate insulating layer;

an oxide semiconductor layer;

a second conductive layer and a third conductive layer electrically connected to the oxide semiconductor layer;

a second insulating layer over the second conductive layer and the third conductive layer;

a second gate insulating layer over the second insulating layer; and

a second gate electrode layer over the second gate insulating layer,

wherein the oxide semiconductor layer comprises an intrinsic or substantially intrinsic oxide semiconductor,

wherein the second gate insulating layer is in contact with the oxide semiconductor layer through an opening provided in the second insulating layer,

wherein the oxide semiconductor layer comprises microcrystalline portions, and

wherein the first insulating layer is provided between the first conductive layer and one of the second conductive layer and the third conductive layer.

2. The semiconductor device according to claim 1 , further comprising a fourth conductive layer electrically connected to one of the second conductive layer and the third conductive layer,

wherein the fourth conductive layer overlaps with the first conductive layer and the first insulating layer.

3. The semiconductor device according to claim 1 , wherein the oxide semiconductor layer contains In, Ga, and Zn.

4. The semiconductor device according to claim 1 , wherein an off-current value of the thin film transistor is less than or equal to 1×10 −13 A.

5. The semiconductor device according to claim 1 , wherein the semiconductor device is a CPU.

6. The semiconductor device according to claim 1 , wherein the semiconductor device is an LSI.

7. The semiconductor device according to claim 1 , wherein the semiconductor device is a DRAM.

8. The semiconductor device according to claim 1 , wherein a hydrogen concentration in the oxide semiconductor layer is lower than or equal to 5×10 19 /cm 3 and a carrier concentration in the oxide semiconductor layer is lower than or equal to 5×10 14 /cm 3 .

9. The semiconductor device according to claim 1 , wherein the opening is provided between the first conductive layer and the second conductive layer.

10. A semiconductor device comprising:

a substrate;

a first conductive layer over the substrate;

a first insulating layer over the first conductive layer; and

a thin film transistor,

wherein the thin film transistor comprises:

a first gate electrode layer;

a first gate insulating layer;

an oxide semiconductor layer adjacent to the first gate electrode layer with the first gate insulating layer interposed therebetween;

a second conductive layer and a third conductive layer electrically connected to the oxide semiconductor layer;

a second insulating layer over and in contact with the second conductive layer and the third conductive layer;

a second gate insulating layer over the second insulating layer; and

a second gate electrode layer over the second gate insulating layer,

wherein the oxide semiconductor layer comprises an intrinsic or substantially intrinsic oxide semiconductor,

wherein the second gate insulating layer is in contact with the oxide semiconductor layer through an opening provided in the second insulating layer,

wherein a relation of E c -E f <E g /2 is satisfied where E c is an energy at a bottom of a conduction band of the oxide semiconductor layer, E f is a Fermi energy of the oxide semiconductor layer, and E g is a band gap of the oxide semiconductor layer, and

wherein the first insulating layer is provided between the first conductive layer and one of the second conductive layer and the third conductive layer.

11. The semiconductor device according to claim 10 , wherein a hydrogen concentration in the oxide semiconductor layer is lower than or equal to 5×10 19 /cm 3 and a carrier concentration in the oxide semiconductor layer is lower than or equal to 5×10 14 /cm 3 .

12. The semiconductor device according to claim 10 , wherein the oxide semiconductor layer contains In, Ga, and Zn.

13. The semiconductor device according to claim 10 , wherein an off-current value of the thin film transistor is less than or equal to 1×10 −13 A.

14. The semiconductor device according to claim 10 , wherein the opening is provided between the first conductive layer and the second conductive layer.

15. A semiconductor device comprising:

an oxide semiconductor layer;

a first conductive layer and a second conductive layer over the oxide semiconductor layer;

an insulating layer over the first conductive layer and the second conductive layer;

a gate insulating layer over the insulating layer; and

a gate electrode layer over the gate insulating layer,

wherein the gate insulating layer is in contact with the oxide semiconductor layer through an opening provided in the insulating layer, and

wherein the opening of the insulating layer overlaps with the oxide semiconductor layer and the gate electrode layer.

16. The semiconductor device according to claim 15 , wherein the opening is provided between the first conductive layer and the second conductive layer.

17. The semiconductor device according to claim 15 , wherein the oxide semiconductor layer contains In, Ga, and Zn.

18. The semiconductor device according to claim 15 , wherein a hydrogen concentration in the oxide semiconductor layer is lower than or equal to 5×10 19 /cm 3 and a carrier concentration in the oxide semiconductor layer is lower than or equal to 5×10 14 /cm 3 .

Assignments (1)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Apr 3, 2014
From: YAMAZAKI, SHUNPEI; KOYAMA, JUN; MIYAKE, HIROYUKI; TAKAHASHI, KEI; TOYOTAKA, KOUHEI; TSUBUKU, MASASHI; NODA, KOSEI; KUWABARA, HIDEAKI
To: SEMICONDUCTOR ENERGY LABORATORY CO., LTD.
Reel/Frame 032594/0468 →
Priority Claims (1)
JP 2009-238885 · Oct 16, 2009 · national
Continuity (2)
Continuation 12904565 · Oct 14, 2010
Related Publication 20130193434A1 · Aug 1, 2013