Multi-tuner using interpolative dividers
An apparatus includes a splitter to receive a radio frequency (RF) signal and to provide the RF signal to multiple channels of a tuner. Each channel may include an amplifier to amplify the RF signal, a mixer to downconvert the amplified RF signal to a second frequency signal using a local oscillator (LO) signal, where each of the channels is configured to receive a different LO signal, a filter to filter the downconverted second frequency signal, and a digitizer to digitize the downconverted second frequency signal. A clock generation circuit has multiple interpolative dividers and a frequency synthesizer to generate a reference clock signal. Each of the interpolative dividers is configured to receive the reference clock signal, generate a corresponding LO signal, and provide the corresponding LO signal to the mixer of at least one of the channels.
1. An apparatus comprising:
a splitter to receive a radio frequency (RF) signal and to provide the RF signal to a plurality of channels, wherein each of the plurality of channels comprises:
a first amplifier to amplify the RF signal;
a mixer to downconvert the amplified RF signal to a second frequency signal using a local oscillator (LO) signal, each of the plurality of channels configured to receive a different LO signal;
a first filter to filter the downconverted second frequency signal;
a digitizer to digitize the downconverted second frequency signal; and
a clock generation circuit including a frequency synthesizer to generate a reference clock signal and a plurality of interpolative dividers, each of the plurality of interpolative dividers to receive the reference clock signal and to generate a corresponding LO signal therefrom and to provide the corresponding LO signal to the mixer of at least one of the plurality of channels.
2. The apparatus of claim 1 , wherein the apparatus comprises a multi-tuner circuit configured on a single semiconductor die.
3. The apparatus of claim 1 , wherein the clock generation circuit comprises a controller coupled to the interpolative divider, wherein the controller is to control a value of the LO signal output by the interpolative divider to cause downconversion of the amplified RF signal to a narrowband signal substantially around DC, wherein a resolution of the interpolative divider is limited to cause spurs generated in the interpolative divider to be maintained away from the LO signal.
4. The apparatus of claim 1 , wherein responsive to the RF signal, the clock generation circuit is to configure a first interpolative divider to operate at a fixed divide ratio.
5. The apparatus of claim 1 , wherein each of the plurality of channels further comprises a second filter coupled between the first amplifier and the mixer.
6. The apparatus of claim 5 , wherein each of the plurality of channels further comprises a second amplifier coupled between the mixer and the first filter.
7. The apparatus of claim 6 , wherein the second filter comprises a tracking bandpass filter and the first filter comprises a low pass filter.
8. The apparatus of claim 1 , wherein the digitizer comprises a narrow band lowpass delta-sigma modulator.
9. The apparatus of claim 1 , wherein the interpolative divider comprises:
a controllable divider to receive the reference clock signal and to generate a divided signal;
a delay element to receive the divided clock signal and to provide a delayed divided clock signal;
an interpolator to receive the divided clock signal and the delayed divided clock signal and to interpolate the divided clock signal and the delayed divided clock signal into a third frequency signal; and
a second divider to divide the third frequency signal to obtain a LO2x signal.
10. The apparatus of claim 9 , wherein the interpolative divider further includes a counter to be clocked by the divided clock signal, and to generate to a control signal to be provided to the controllable divider, wherein the control signal is to cause the controllable divider to change a divide ratio from N to N+1.
11. The apparatus of claim 9 , wherein the interpolator comprises:
a plurality of current digital-to-analog converters (DACs); and
a capacitor to integrate an output of the plurality of current DAC circuits.
12. The apparatus of claim 11 , wherein the second divider comprises:
a comparator to compare an integrating voltage of the capacitor to a threshold voltage; and
a second delay element clocked by an output of the comparator.
13. The apparatus of claim 1 , wherein responsive to a user request for a first analog channel, at least one of the interpolative dividers is to operate as a M-level interpolator when the downconverted second frequency signal falls substantially around DC, and responsive to a user request for a digital channel, the at least one interpolative divider is configured to operate as a M/2-level interpolator.
14. A system comprising:
an integrated circuit (IC) multi-tuner circuit having a first semiconductor die including a first tuner to receive and process a radio frequency (RF) signal to output a first digitized signal and a second tuner to receive and process the RF signal to output a second digitized signal;
a clock generation circuit including a single frequency synthesizer to generate a reference clock signal and a plurality of interpolative dividers each including an interpolator having M-levels of resolution, each of the plurality of interpolative dividers to receive the reference clock signal and to generate a corresponding LO signal therefrom according to a fixed divide ratio and to provide the corresponding LO signal to one of the first and second tuners, wherein the corresponding interpolator is configured to operate as a M/2-level interpolator when a desired channel is a digital channel and as a M-level interpolator when the desired channel is an analog channel; and
a demodulator coupled to receive and demodulate the first and second digitized signals.
15. The system of claim 14 , wherein the first tuner further comprises:
a first amplifier to amplify the RF signal;
a mixer to downconvert the amplified RF signal to a second frequency signal using the corresponding LO signal;
a first filter to filter the downconverted second frequency signal; and
a digitizer to digitize the downconverted second frequency signal.
16. The system of claim 15 , wherein the clock generation circuit comprises a controller coupled to the plurality of interpolative dividers, wherein the controller is to control a value of the LO signal output by a first interpolative divider to cause downconversion of the amplified RF signal to a narrowband signal substantially around DC, wherein a resolution of the interpolative divider is limited to cause spurs generated in the interpolative divider to be maintained away from the LO signal.
17. A method comprising:
configuring an interpolative divider of a clock generation circuit of a television tuner integrated on a single semiconductor die as a M/2-level interpolator responsive to a request to tune to a desired channel corresponding to a digital channel;
controlling the interpolative divider to generate a local oscillator (LO) signal from a reference clock signal according to a fixed divide ratio and providing the LO signal to a first tuner of a plurality of tuners of the television tuner; and
downconverting and processing the RF signal in the first tuner using the LO signal.
18. The method of claim 17 , further comprising configuring the interpolative divider as a M-level interpolator responsive to a request to tune to a second desired channel corresponding to an analog channel.
19. The method of claim 18 , further comprising determining if a downconverted signal from the analog channel would be substantially around DC, and if so, configuring the interpolative divider as the M-level interpolator.
20. The method of claim 19 , further comprising otherwise configuring the interpolative divider as the M/2-level interpolator.