Stride-based translation lookaside buffer (TLB) prefetching with adaptive offset

1. A processing device, comprising:

a data prefetcher to generate a data prefetch address based on at least one of a linear address, a stride, or a prefetch distance, the data prefetch address associated with a data prefetch request;

a translation lookaside buffer (TLB) prefetch address computation component communicably coupled to the data prefetcher, the TLB prefetch address computation component to generate a TLB prefetch address based on at least one of the linear address, the stride, the prefetch distance, or an adaptive offset; and

a cross page detection component communicably coupled to the data prefetcher and the TLB prefetch address computation component, the cross page detection component to:

determine that the data prefetch address or the TLB prefetch address cross a page boundary associated with the linear address; and

cause a TLB prefetch request to be written to a TLB request queue based on determining that the data prefetch address or the TLB prefetch address cross the page boundary associated with the linear address, the TLB prefetch request for translation of an address of a linear page number (LPN) that is based on at least one of the data prefetch address or the TLB prefetch address.

2. The processing device of claim 1 , wherein the TLB prefetch request in the TLB request queue is sent to a TLB for the translation of the address.

3. The processing device of claim 1 , wherein the TLB request queue further comprises a TLB prefetch request queue and a TLB lookup request queue;

wherein the TLB prefetch request queue to store one or more TLB prefetch requests for LPNs generated based on the TLB prefetch address; and

wherein the TLB lookup request queue to store one or more TLB prefetch requests for LPNs generated based on the data prefetch address.

4. The processing device of claim 1 , wherein when the TLB prefetch address is determined to cross the page boundary, the cross page detection component further to set a first cross page flag to indicate occurrence of a first prefetch condition.

5. The processing device of claim 4 , wherein when the first cross page flag is set to indicate the occurrence of the first prefetch condition, the TLB prefetch address is concatenated with the linear page address to generate the LPN for the TLB prefetch request.

6. The processing device of claim 1 , wherein when the data prefetch address is determined to cross the page boundary, the cross page detection component further to set a second cross page flag to indicate occurrence of a second prefetch condition.

7. The processing device of claim 6 , wherein when the second cross page flag is set to indicate the occurrence of the second prefetch condition, the data prefetch address is concatenated with the linear page address to generate the LPN for the TLB prefetch request.

8. The processing device of claim 6 , wherein when the second prefetch condition occurs, the cross page detection component to increment an adaptive offset counter.

9. The processing device of claim 8 , wherein when the adaptive offset counter exceeds an adaptive offset counter threshold and when a value of the adaptive offset is less than an adaptive offset limit, the adaptive offset is increased.

10. A method, comprising:

receiving, by a translation lookaside buffer (TLB) prefetch component of a processing device, a data prefetch address based on at least one of a linear address, a stride, or a prefetch distance, the data prefetch address associated with a data prefetch request;

generating a TLB prefetch address based on at least one of the linear address, the stride, the prefetch distance, or an adaptive offset;

determining that the data prefetch address or the TLB prefetch address cross a page boundary associated with the linear address; and

writing a TLB prefetch request to a TLB request queue based on determining that the data prefetch address or the TLB prefetch address cross the page boundary associated with the linear address, the TLB prefetch request for translation of an address of a linear page number (LPN) that is based on at least one of the data prefetch address or the TLB prefetch address.

11. The method of claim 10 , further comprising, sending the TLB prefetch request in the TLB request queue is sent to a TLB for the translation of the address.

12. The method of claim 10 , wherein the TLB request queue further comprises:

a TLB prefetch request queue to store one or more TLB prefetch requests for LPNs generated based on the TLB prefetch; and

a TLB lookup request queue to store one or more TLB prefetch requests for LPNs generated based on the data prefetch address.

13. The method of claim 10 , further comprising when the TLB prefetch address is determined to cross the page boundary, setting a first cross page flag to indicate occurrence of a first prefetch condition.

14. The method of claim 13 , further comprising when the first cross page flag is set to indicate the occurrence of the first prefetch condition, concatenating the TLB prefetch address with the linear page address to generate the LPN for the TLB prefetch request.

15. The method of claim 10 , further comprising when the data prefetch address is determined to cross the page boundary, setting a second cross page flag to indicate occurrence of a second prefetch condition.

16. The method of claim 15 , further comprising when the second cross page flag is set to indicate the occurrence of the second prefetch condition, concatenating the data prefetch address with the linear page address to generate the LPN for the TLB prefetch request.

17. The method of claim 15 , further comprising when the second prefetch condition occurs, incrementing an adaptive offset counter.

18. The method of claim 17 , wherein when the adaptive offset counter exceeds an adaptive offset counter threshold and when a value of the adaptive offset is less than an adaptive offset limit, increasing the adaptive offset.

19. An system comprising:

a memory;

a processing device communicably coupled to the memory, the processing device comprising a translation-lookaside buffer (TLB) prefetch component to:

receive a data prefetch address based on at least one of a linear address, a stride, or a prefetch distance, the data prefetch address associated with a data prefetch request;

generate a TLB prefetch address based on at least one of the linear address, the stride, the prefetch distance, or an adaptive offset;

determine that the data prefetch address or the TLB prefetch address cross a page boundary associated with the linear address; and

send a TLB prefetch to a TLB of the processing device based on determining that the data prefetch address or the TLB prefetch address cross the page boundary associated with the linear address, the TLB prefetch request for translation of an address of a linear page number (LPN) that is based on at least one of the data prefetch address or the TLB prefetch address.

20. The system of claim 19 , wherein the TLB request is sent from a TLB request queue that comprises:

a TLB prefetch request queue to store one or more TLB prefetch requests for LPNs generated based on the TLB prefetch; and

a TLB lookup request queue to store one or more TLB prefetch requests for LPNs generated based on the data prefetch address.

21. The system of claim 19 , further comprising when the TLB prefetch address is determined to cross the page boundary, the processing device to set a first cross page flag to indicate occurrence of a first prefetch condition.

22. The system of claim 21 , further comprising when the first cross page flag is set to indicate the occurrence of the first prefetch condition, the processing device to concatenate the TLB prefetch address with the linear page address to generate the LPN for the TLB prefetch request.

23. The system of claim 19 , further comprising when the data prefetch address is determined to cross the page boundary, the processing device to set a second cross page flag to indicate occurrence of a second prefetch condition.

24. The system of claim 23 , further comprising when the second cross page flag is set to indicate the occurrence of the second prefetch condition, the processing device to concatenate the data prefetch address with the linear page address to generate the LPN for the TLB prefetch request.