Methods and systems for devices with self-selecting bus decoder
Disclosed are methods and devices, among which is a device including a self-selecting bus decoder. In some embodiments, the device may be coupled to a microcontroller, and the self-selecting bus decoder may determine a response of the peripheral device to requests from the microcontroller. In another embodiment, the device may include a bus translator and a self-selecting bus decoder. The bus translator may be configured to translate between signals from a selected one of a plurality of different types of buses. A microcontroller may be coupled to a selected one of the plurality of different types of buses of the bus translator.
1. A system, comprising:
a microcontroller; and
a device coupled to the microcontroller via a bus, wherein the device comprises a self-selecting bus decoder configured to:
receive a memory mapping configuration;
receive a request from the microprocessor; and
determine if the device should provide a response to the request from the microcontroller, based at least in part upon the memory mapping configuration.
2. The system of claim 1 , wherein the device comprises a pattern recognition processor.
3. The system of claim 1 , wherein the decoder is configured to receive the memory mapping configuration via a decode set-up and control signal independent from the request.
4. The system of claim 1 , wherein the memory mapping configuration comprises an indication of a plurality of memory addresses provided by the device.
5. The system of claim 1 , wherein the memory mapping configuration comprises an indication of a plurality of memory addresses provided by the microcontroller.
6. The system of claim 1 , wherein the decoder is configured to determine that the device should provide the response when a memory address associated with the request is provided by the device based on the memory mapping configuration.
7. The system of claim 1 , wherein the device comprises double data rate two (DDR2) RAM.
8. The system of claim 1 , wherein the request comprises a memory read, a memory write, a memory refresh, a DMA request, or any combination thereof.
9. The system of claim 3 , wherein the decoder is configured to determine a type of the request.
10. The system of claim 3 , wherein the decoder is configured to determine a response to the request.
11. A method, comprising:
receiving a request from a microcontroller via a bus;
determining a memory address of the request;
determining if the memory address is provided by an external device coupled to the microcontroller via the bus;
determining a type of the memory request; and
determining a response to the memory request.
12. The method of claim 11 , comprising providing a response from the external device to the microcontroller.
13. The method of claim 11 , comprising receiving a memory mapping configuration at the external device.
14. The method of claim 12 , comprising providing data from the external device.
15. The method of claim 12 , wherein determining a response to the memory request comprises selecting a function of the external device.
16. A device, comprising:
a self-selecting bus decoder comprising logic configured to:
receive a memory mapping configuration;
receive a request via a microcontroller bus; and
determine if the device should provide a response to the request, based at least in part upon the memory mapping configuration.
17. The device of claim 16 , comprising logic to determine a type of the request and a response to the request.
18. The device of claim 16 , comprising logic configured to provide a signal to enable the device to respond to the request.
19. The device of claim 16 , wherein the decoder is configured to receive a memory mapping configuration.
20. The device of claim 16 , wherein the decoder is configured to determine that the device should provide the response when a memory address associated with the request is associated with at least one of a plurality of memory addresses indicated by the memory mapping configuration.
21. A device, comprising:
a pattern-recognition processor; and
a decoder comprising logic configured to:
select the device in response to a request from a microcontroller coupled to the device; and
determine if a memory address received from the microcontroller is provided by the device.