Embodiments provide a limiter circuit that includes a power splitter coupled with a plurality of antiparallel diode pairs. In some embodiments, the power splitter may be part of a first stage of the limiter circuit. Other embodiments may be described and claimed.
1. A limiter circuit comprising:
an input node;
a power splitter coupled with the input node and having a plurality of parallel branches;
a plurality of antiparallel diode pairs respectively coupled between the plurality of parallel branches of the power splitter and ground or a voltage source; and
an output node coupled with the power splitter.
2. The limiter circuit of claim 1 , wherein the plurality of antiparallel diode pairs are configured to limit a power of a radio frequency signal provided to the output node.
3. The limiter circuit of claim 1 , wherein the plurality of antiparallel diode pairs include vertical P-I-N diodes.
4. The limiter circuit of claim 3 , wherein the vertical P-I-N diodes comprise gallium arsenide vertical P-I-N diodes.
5. The limiter circuit of claim 1 , further comprising:
a transmission line coupled with the output node and the power splitter;
a first stage including the power splitter and the plurality antiparallel diode pairs; and
a second stage including a second stage antiparallel diode pair comprising:
a first diode with a cathode coupled with the transmission line and an anode coupled with the ground or the voltage source; and
a second diode with an anode coupled with the transmission line and a cathode coupled with the ground or the voltage source.
6. The limiter circuit of claim 1 , further comprising:
a transmission line coupled with the output node and the power splitter;
an input stage including the power splitter, the first antiparallel diode pair, and the second antiparallel diode pair; and
one or more additional stages, wherein individual stages of the one or more additional stages include antiparallel diode pairs coupled with the transmission line.
7. The limiter circuit of claim 1 , wherein the power splitter comprises at least three parallel branches and at least three antiparallel diode pair respectively coupled with the at least three parallel branches.
8. The limiter circuit of claim 1 , wherein at least one diode within the plurality of antiparallel diode pairs comprises a plurality of diodes that are coupled in series.