Suppressed carrier harmonic amplitude modulator
View Patent ↗A circuit includes a switched modulator stage combining an information signal with a square wave carrier to produce a first modulated signal; and a second modulation stage forming additional steps in the first modulated signal to produce a second modulated signal.
1. A switched modulator, comprising:
a first modulation stage configured to combine an information signal with a square wave carrier to form a first modulated signal; and
a second modulation stage configured to insert additional steps in the first modulated signal to form a second modulated signal that is a finer approximation of a sinusoidal wave than the first modulated signal.
2. The switched modulator of claim 1 , further comprising:
the second modulation stage configured to modify the first modulated signal into a three-step approximation of the sinusoidal wave.
3. The switched modulator of claim 1 , further comprising:
the second modulation stage configured to modify the first modulated signal into a four-step approximation of the sinusoidal wave.
4. The switched modulator of claim 2 , further comprising:
the second modulation stage configured to blank the first modulated signal at an interval around a zero crossing of the first modulated signal.
5. The switched modulator of claim 3 , further comprising:
the second modulation stage configured to modify the first modulation signal at an interval around a zero crossing of the first modulated signal with a voltage selected from a plurality of taps of a voltage ladder.
6. The switched modulator of claim 1 , further comprising:
the second modulation stage comprising a multiplexer configured to be controlled by a selection signal that is synchronous with a two-step square wave that is combined with the information signal in the first modulation stage to form the first modulated signal.
7. The switched modulator of claim 1 , further comprising:
the switched modulator configured to modify the second modulated signal into a sinusoidal wave approximation having a ⅔ half-wave duty cycle.
8. The switched modulator of claim 1 , further comprising:
the switched modulator configured to modify the second modulated signal into a sinusoidal wave approximation having a ⅘ half-wave duty cycle.
9. A method of producing a modulated output signal, comprising:
combining an information signal in a first modulator stage with a square wave carrier to form a first modulated signal; and
modifying the first modulated signal in a second modulator stage into a finer approximation of a sinusoidal wave to produce the modulated output signal by inserting additional steps in the first modulated signal.
10. The method of claim 9 , further comprising:
modifying the first modulated signal in the second modulation stage into a three-step approximation of the sinusoidal wave.
11. The method of claim 9 , further comprising:
modifying the first modulated signal in the second modulation stage into a four-step approximation of the sinusoidal wave.
12. The method of claim 10 , further comprising:
blanking the first modulated signal in the second modulation stage at an interval around a zero crossing of the first modulated signal.
13. The method of claim 11 , further comprising:
selecting a voltage from among taps of a voltage ladder in the second modulation stage at an interval around a zero crossing of the first modulated signal.
14. The method of claim 9 , further comprising:
controlling a multiplexer in the second stage using a selection signal that is synchronous with the square wave that is combined with the information signal in the first modulation stage.
15. A circuit, comprising:
a first modulation stage comprising a switched modulator circuit configured to combine an information signal with a square wave carrier to produce a first modulated signal; and
a second modulation stage configured to receive the first modulated signal and form additional steps in the first modulated signal to produce a second modulated signal.
16. The circuit of claim 15 , further comprising:
the second modulation stage configured to form an additional two steps in each half-wave of the first modulated signal.
17. The circuit of claim 15 , further comprising:
the second modulation stage configured to form an additional four steps in each half-wave of the first modulated signal.
18. The circuit of claim 16 , further comprising:
the second modulation stage configured to blank the first modulated signal at an interval around a zero crossing of the first modulated signal.
19. The circuit of claim 17 , further comprising:
the second modulation stage configured to select for the second modulated signal a voltage from one of a plurality of taps of a voltage ladder at an interval around a zero crossing of the first modulated signal.
20. The circuit of claim 15 , further comprising:
the second modulation stage comprising a multiplexer configured to be controlled by a selection signal that is synchronous with the square wave that is combined with the information signal in the first modulation stage.