Selective self-reference read
View Patent ↗This disclosure relates to selectively performing a read with increased accuracy, such as a self-reference read, from a memory. In one aspect, data is read from memory cells, such as magnetoresitive random access memory (MRAM) cells, of a memory array. In response to detecting a condition associated with reading from the memory cells, a self-reference read can be performed from at least one of the memory cells. For instance, the condition can indicate that data read from the memory cells is uncorrectable via decoding of error correction codes (ECC). Selectively performing self-reference reads can reduce power consumption and/or latency associated with reading from the memory compared to always performing self-reference reads.
1. A method of reading data from a memory array, the method comprising:
reading data from memory cells of the memory array; and
in response to determining that an error in the data read from the memory cells is uncorrectable via error correction codes, performing a self-reference read from the same memory cells, wherein the self-reference read comprises comparing a value read from a memory cell to another value read from the same memory cell.
2. The method of claim 1 , wherein a first latency in providing valid data read from the memory cells to a processor associated with said reading is less than a second latency in providing valid data read from the same memory cells to the processor in said performing the self-reference read.
3. The method of claim 1 , wherein a first latency in providing valid data read from the memory cells to a processor associated with said reading is approximately the same as a second latency in providing valid data read from the same memory cells to the processor in said performing the self-reference read.
4. The method of claim 1 , wherein the memory cells comprise magnetoresistive random access memory (MRAM) cells.
5. The method of claim 1 , wherein more than one codeword is read at a time, wherein performing the self-reference read further comprises performing a self-reference read only on digits of a codeword identified as having been read with an uncorrectable error.
6. The method of claim 1 , wherein preforming the self-reference read further comprises re-programming the memory cell when comparing the value read from the memory cell to the another value read from the same memory cell indicates that the compared values correspond to different states of the memory cell.
7. The method of claim 1 , further comprising correcting correctable errors in the data read from the memory cells via decoding of error correction codes.
8. The method of claim 1 , further comprising providing the data from said reading to a processor in response to determining that all errors in the data are correctable via error correction codes.
9. A method of reading data from a memory array, the method comprising:
reading data from memory cells of the memory array by comparing values associated with the memory cells of the memory array with a reference value;
in response to detecting a condition associated with said reading, performing a self-reference read from at least one of the memory cells, wherein the self-reference read comprises comparing a value read from a memory cell to another value read from the same memory cell; and
accessing, by a processor, data from the memory array with a variable latency, wherein data accessed by said reading has a lower latency than data accessed by said performing the self-reference read.
10. The method of claim 9 , wherein each of the memory cells comprises a memory element configured to have a different resistance in a first state than in a second state.
11. The method of claim 10 , wherein performing the self-reference read comprises:
programming a selected memory cell to the first state; and
re-programming the selected memory cell to the second state when comparing the value read from the selected memory cell to the another value read from the selected memory cell indicates that one of the compared values corresponds to the first state and the other of the compared values corresponds to the second state.
12. The method of claim 9 , wherein the memory cells comprise magnetic tunnel junction spin torque transfer magnetoresistive random access memory (MTJ STT-MRAM) cells.
13. The method of claim 9 , further comprising correcting one or more errors in the data read from the memory cells via error correction codes when the condition is not detected.
14. The method of claim 9 , further comprising correcting errors in the data from said reading via error correction codes, and providing the corrected data to a processor when no errors are detected in the corrected data.
15. The method of claim 9 , wherein the reference value is generated by a reference cell comprising a memory cell having a resistive circuit element.
16. The method of claim 9 , wherein the condition is indicative of at least one suspected error in the data read from the memory cells.
17. The method of claim 9 , wherein the memory cells comprise magnetoresistive random access memory (MRAM) cells.
18. The method of claim 9 , wherein the condition is indicative of an error in the data read from the memory cells being uncorrectable via error correction codes.
19. The method of claim 9 , wherein the condition is indicative of a number of errors in the data read from the memory cells having at least a threshold number of errors, and wherein the threshold number of errors is greater than 1.
20. An apparatus comprising:
a memory array comprising memory cells, the memory array configured to store codewords comprising data and corresponding error correction codes;
an error correction encoder/decoder configured to generate error correction codes, to identify errors in codewords, and to correct errors in codewords; and
a sense circuit having a first mode and a second mode, wherein the second mode is activated only when errors in a codeword are determined to be uncorrectable, the sense circuit comprising:
a reference circuit configured to generate a reference signal for the first mode;
a self-reference circuit configured to receive a value read from a selected memory cell of the memory array associated with a first read operation, and to generate a self-reference signal based on the received value for the second mode; and
a sense output circuit configured to:
perform a first comparison of the value read from the selected memory cell of the memory array associated with the first read operation with the reference signal;
perform a second comparison of the a value read from the selected memory cell of the memory array associated with a second read operation with the self-reference value, the second read operation occurring subsequent to the first read operation; and
output a data digit based on a select signal and at least one of the first comparison or the second comparison, the data digit representing data stored in the selected memory cell.
21. The apparatus of claim 20 , wherein the sense output circuit is configured to perform either the first comparison or the second comparison based on the select signal.
22. The apparatus of claim 20 , wherein the sense output circuit comprises a sense amplifier configured to determine the data digit.
23. The apparatus of claim 22 , wherein the sense output circuit further comprises a multiplexer configured to provide either the reference signal or the self-reference signal to the sense amplifier based on the select signal.
24. The apparatus of claim 20 , wherein the memory cells comprise magnetoresistive random access memory (MRAM) cells.
25. The apparatus of claim 20 , wherein the error correction code encoder/decoder is further configured to correct one or more errors in the data digits read by the sense circuit.
26. The apparatus of claim 25 , wherein the error correction code encoder/decoder and the memory array are included on a single die.
27. The apparatus of claim 20 , wherein the apparatus is further configured to generate a data ready signal indicative of whether the data digit is valid.
28. A method of reading data from a memory array, the method comprising:
reading data from memory cells of the memory array by comparing values associated with the memory cells of the memory array with a reference value; and
in response to detecting a condition associated with said reading, performing a self-reference read from at least one of the memory cells, wherein the self-reference read comprises comparing a value read from a memory cell to another value read from the same memory cell, and wherein the condition is indicative of at least one of an error in the data read from the memory cells being uncorrectable via error correction codes or a number of errors in the data read from the memory cells having at least a threshold number of errors that is greater than 1.
29. The method of claim 28 , wherein the memory cells comprise magnetoresistive random access memory (MRAM) cells.
30. The method of claim 28 , wherein the condition is indicative of an error in the data read from the memory cells being uncorrectable via error correction codes.
31. The method of claim 30 , further comprising providing the data from said reading to a processor in response to determining that all errors in the data are correctable via error correction codes.
32. The method of claim 28 , wherein the condition is indicative of a number of errors in the data read from the memory cells having at least a threshold number of errors, and wherein the threshold number of errors is greater than 1.