IP Library Granted Patent US 9,367,342
Granted Patent B2
US 9,367,342 · App. 13/817,278 · Granted Jun 14, 2016

Optimizing a deactivation process for a virtual machine system

Inventor: Tetsuji Yamamoto (Osaka, JP)
Assignee: PANASONIC INTELLECTUAL PROPERTY CORPORATION OF AMERICA
G06F9/45533G06F1/3287G06F9/485G06F9/4893G06F2209/482Y02B60/1282Y02B60/144
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Quick Facts
Patent No.
US 9,367,342
App. No.
13/817,278
Granted
Jun 14, 2016
Kind
B2
Abstract

A virtual machine system includes one or more virtual machines and a deactivator that deactivates the virtual machines. Each virtual machine includes an output unit that outputs a deactivation prohibiting signal indicating that the virtual machine is not permitted to stop operating while deactivation prohibited processing is being executed. The deactivation prohibited processing is processing that involves the device and during which the virtual machine is not permitted to stop operating. The deactivator deactivates a virtual machine that has not output the deactivation prohibiting signal, and does not deactivate a virtual machine that has output the deactivation prohibiting signal.

Claims (30)

1. A virtual machine system for implementing one or more virtual machines and a deactivator that deactivates the one or more virtual machines, the virtual machine system comprising:

a processor utilizing a device; and

a memory storing therein a program executed by the processor, the virtual machine system causing the processor to execute the program stored in the memory to implement the one or more virtual machines and the deactivator, wherein

the deactivator includes a deactivating signal output unit that outputs a deactivating signal to each of the one of more virtual machines, the deactivating signal instructing each of the one or more virtual machines to stop operating,

each of the one or more virtual machines includes an output unit that outputs, in response to receiving the deactivating signal output from the deactivating signal output unit, a deactivation prohibiting signal while the virtual machine is executing deactivation prohibited processing, the deactivation prohibited processing being processing that involves the device and during which the virtual machine is not permitted to stop operating, the deactivation prohibiting signal indicating that the virtual machine is not permitted to stop operating,

the deactivator (i) deactivates a virtual machine that does not output the deactivation prohibiting signal in response to receiving the deactivating signal output from the deactivating signal output unit, and (ii) does not deactivate a virtual machine that outputs the deactivation prohibiting signal in response to receiving the deactivating signal output from the deactivating signal output unit,

each of the one or more virtual machines includes a processing time reducing unit that, when the virtual machine is executing the deactivation prohibited processing in response to receiving the deactivating signal output from the deactivating signal output unit, performs processing time reduction processing of reducing processing time required until termination of the deactivation prohibited processing,

the deactivation prohibited processing includes update processing involving at least one of (i) processing that, when terminated due to interruption, physically damages the device and (ii) processing that, when terminated due to interruption, disables correct reading of data from the device,

the processing time reduction processing is executable when the update processing has not been completed, and

the processing time reduction processing terminates the deactivation prohibited processing even when the deactivation prohibited processing has not completed and starts execution of recovery processing at highest execution priority, the recovery processing only including the update processing associated therewith among the deactivation prohibited processing.

2. The virtual machine system of claim 1 , further comprising:

a power controller that controls power supplied to the processor, wherein

the deactivator includes a power stop unit that causes, when all of the virtual machines implemented by the processor stop operating, the processor to transmit, to the power controller, a power stopping signal indicating that power supplied to the processor is to be stopped, and

when the power stopping signal is transmitted from the processor, the power controller stops the power supplied to the processor.

3. A virtual machine system control method for controlling a virtual machine system for implementing one or more virtual machines and a deactivator that deactivates the one or more virtual machines, the virtual machine system including (i) a processor utilizing a device, and (ii) a memory storing therein a program executed by the processor, the virtual machine system causing the processor to execute the program stored in the memory to implement the one or more virtual machines and the deactivator, the virtual machine system control method comprising:

outputting a deactivating signal from the deactivator to each of the one of more virtual machines, the deactivating signal instructing each of the one or more virtual machines to stop operating;

outputting, from each of the one or more virtual machines to the deactivator in response to receiving the deactivating signal from the deactivator, a deactivation prohibiting signal while the virtual machine is executing deactivation prohibited processing, the deactivation prohibited processing being processing that involves the device and during which the virtual machine is not permitted to stop operating, the deactivation prohibiting signal indicating that the virtual machine is not permitted to stop operating;

causing the deactivator to (i) deactivate a virtual machine that does not output the deactivation prohibiting signal in response to receiving the deactivating signal output from the deactivator, and (ii) does not deactivate a virtual machine that outputs the deactivation prohibiting signal in response to receiving the deactivating signal output from deactivator; and

performing, for each of the one or more virtual machines when the virtual machine is executing the deactivation prohibited processing in response to receiving the deactivating signal output from the deactivator, processing time reduction processing of reducing processing time required until termination of the deactivation prohibited processing, wherein

the deactivation prohibited processing includes update processing involving at least one of (i) processing that, when terminated due to interruption, physically damages the device and (ii) processing that, when terminated due to interruption, disables correct reading of data from the device,

the processing time reduction processing is executable when the update processing has not been completed, and

the processing time reduction processing terminates the deactivation prohibited processing even when the deactivation prohibited processing has not completed and starts execution of recovery processing at highest execution priority, the recovery processing only including the update processing associated therewith among the deactivation prohibited processing.

4. A non-transitory computer readable recoding medium having stored thereon a virtual machine system control program for causing a virtual machine system implementing one or more virtual machines and a deactivator that deactivates the one or more virtual machines to execute a virtual machine system control processing of controlling the virtual machine system, the virtual machine system including (i) a processor utilizing a device, and (ii) a memory storing therein a program executed by the processor, the virtual machine system causing the processor to execute the program stored in the memory to implement the one or more virtual machines and the deactivator, the virtual machine system control processing comprising:

outputting a deactivating signal from the deactivator to each of the one of more virtual machines, the deactivating signal instructing each of the one or more virtual machines to stop operating;

outputting, from each of the one or more virtual machines to the deactivator in response to receiving the deactivating signal from the deactivator, a deactivation prohibiting signal while the virtual machine is executing deactivation prohibited processing, the deactivation prohibited processing being processing that involves the device and during which the virtual machine is not permitted to stop operating, the deactivation prohibiting signal indicating that the virtual machine is not permitted to stop operating;

causing the deactivator to (i) deactivate a virtual machine that does not output the deactivation prohibiting signal in response to receiving the deactivating signal output from the deactivator, and (ii) does not deactivate a virtual machine that outputs the deactivation prohibiting signal in response to receiving the deactivating signal output from deactivator; and

performing, for each of the one or more virtual machines when the virtual machine is executing the deactivation prohibited processing in response to receiving the deactivating signal output from the deactivator, processing time reduction processing of reducing processing time required until termination of the deactivation prohibited processing, wherein

the deactivation prohibited processing includes update processing involving at least one of (i) processing that, when terminated due to interruption, physically damages the device and (ii) processing that, when terminated due to interruption, disables correct reading of data from the device,

the processing time reduction processing is executable when the update processing has been not completed, and

the processing time reduction processing terminates the deactivation prohibited processing even when the deactivation prohibited processing has not completed and starts execution of recovery processing at highest execution priority, the recovery processing only including the update processing associated therewith among the deactivation prohibited processing.

Assignments (3)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Nov 28, 2016
From: PANASONIC INTELLECTUAL PROPERTY CORPORATION OF AMERICA
To: SUN PATENT TRUST
Reel/Frame 040419/0979 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded May 27, 2014
From: PANASONIC CORPORATION
To: PANASONIC INTELLECTUAL PROPERTY CORPORATION OF AMERICA
Reel/Frame 033033/0163 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jan 20, 2014
From: YAMAMOTO, TETSUJI
To: PANASONIC CORPORATION
Reel/Frame 032005/0344 →
Priority Claims (1)
JP 2011-256227 · Nov 24, 2011 · national
Continuity (1)
Related Publication 20140089920A1 · Mar 27, 2014