Multi-processor electronic systems
Disclosed herein is a system having a multi-processor configuration for electronics devices and systems, such as, computing and communication devices like laptop, notebook, tablets, smartphones, etc. In accordance with one embodiment of the subject matter the system comprises a plurality of processors and a multi protocol multi-root input output virtualization (MPMRIOV) switch communicatively coupled to at least one of the plurality of processors. The system further includes a peripheral and interface virtualization unit (PIVU) coupled to the MPMRIOV switch. In said embodiment, the PIVU is configured to communicatively couple at least one of the plurality of processors with at least one of a Peripheral Component Interconnect (PCI) compliant peripheral, a Peripheral Component Interconnect express (PCIe) compliant peripheral, a non PCI compliant peripheral, and a non PCIe compliant peripheral.
1. A system comprising:
a plurality of processors, wherein each of the plurality of processors is configured to run an operating system, such that a plurality of operating systems of the system comprises at least one of a homogeneous operating system or a heterogeneous operating system; and
a multiprotocol multi-root input output virtualization (MPMRIOV) switch communicatively coupled to at least one of the plurality of processors;
an Inter Processor Communication unit (IPC) that is configured to enable message exchange between the plurality of processors, wherein the IPC facilitates inter-processor communication between at least two processors of the plurality of processors; and
a peripheral and interface virtualization unit (PIVU) directly coupled to the MPMRIOV switch, wherein the PIVU is configured to communicatively couple at least one of the plurality of processors with at least one of a Peripheral Component Interconnect (PCI) compliant peripheral, a Peripheral Component Interconnect express (PCIe) compliant peripheral, a non PCI compliant peripheral or a non PCIe compliant peripheral, wherein the PIVU is configured to communicatively couple at least one of the processors from amongst the plurality of processors with at least one of the non PCI compliant peripheral or the non PCIe compliant peripheral by implementing at least one of a PCI register set or a PCIe register set, and wherein the system facilitates seamless switching from a first operating system of the plurality of operating systems to a second operating system of the plurality of operating systems.
2. The system as claimed in claim 1 , wherein the plurality of processors comprises at least one of a homogeneous processor or a heterogeneous processor.
3. The system as claimed in claim 1 , wherein the system further facilitates selection of one of the plurality of operating systems as a primary operating system.
4. The system as claimed in claim 1 , wherein the system further facilitates concurrent operation of the plurality of operating systems.
5. The system as claimed in claim 1 , wherein the system is further configured to facilitate at least one of a serial sharing or a parallel sharing of at least one peripheral among the plurality of processors.
6. The system as claimed in claim 1 , wherein at least one of the plurality of processors is configured to exclusively control at least one peripheral.
7. The system as claimed in claim 1 , further comprising a root port configured to communicative couple the system with one or more computing systems.
8. The system as claimed in claim 7 , wherein the root port is further configured to facilitate sharing of at least one peripheral with one or more computing systems.
9. The system as claimed in claim 1 , wherein the MPMRIOV switch is further configured to assign at least one peripheral to at least one of the plurality of processors in at least one of a shared mode or an exclusive mode.
10. The system as claimed in claim 9 , wherein the assignment is further based in part on at least one of a user input, a request from at least one operating system, or a request from an application software.
11. A method for switching from a first operating system that is running on a first processor to a second operating system that is running on a second processor in a multi-processor system that includes a PIVU to communicatively couple at least one of the first processor or the second processor with at least one of a Peripheral Component Interconnect (PCI) compliant peripheral, a Peripheral Component Interconnect express (PCIe) compliant peripheral, a non PCI compliant peripheral, or a non PCIe compliant peripheral, the method comprising:
receiving an input to operate the second operating system that is running on the second processor while operating the first operating system that is running on the first processor;
context exchanging the first operating system that is running on the first processor;
switching the first operating system that is running on the first processor to a low power state; and
operating the second operating system that is running on the second processor in a full power state.
12. The method as claimed in claim 11 , wherein the low power state includes at least one of a stand by mode, a hibernation mode, or a shutdown mode.
13. The method as claimed in claim 11 , wherein the switching further comprises transferring an ownership of at least one of the PCI compliant peripheral, the PCIe compliant peripheral, the non PCI compliant peripheral, or the non PCIe compliant peripheral from the first operating system to the second operating system.
14. The method as claimed in claim 11 , wherein the receiving the input comprises at least one of a trigger or a user input, wherein the trigger comprises at least one of a power state of the multi-processor system or a docking status of the multi-processor system.
15. The method as claimed in claim 11 , wherein the context exchanging further comprises transfer of information from the first operating system to the second operating system.