IP Library Granted Patent US 8,996,734
Granted Patent B2
US 8,996,734 · App. 13/817,822 · Granted Mar 31, 2015

I/O virtualization and switching system

Inventors: Balaji Kanigicherla (Andhra Pradesh, IN); Siva Raghu Ram Voleti (Hyderabad, IN); Krishna Mohan Tandaboina (Hyderabad, IN)
Assignee: Ineda Systems Pvt. Ltd
G06F13/364G06F13/105G06F9/4411
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Quick Facts
Patent No.
US 8,996,734
App. No.
13/817,822
Granted
Mar 31, 2015
Kind
B2
Abstract

Described herein is a system ( 102 ) having a virtualization and switching system configured to virtualize I/O devices ( 108 ) and perform switching of the I/O devices ( 108 ) and I/O requests. The virtualization and switching system ( 102 ) includes a peripheral virtualization controller (PVC) ( 204 ), at least one device control module ( 206 ) connected to the PVC ( 204 ), and at least one command parser ( 210 ). The PVC ( 204 ) is configured to manage I/O virtualization and I/O command access of different I/O devices ( 108 ). The device control module ( 206 ) is configured to store configuration and I/O device registers, implemented by the PVC ( 204 ) to enable virtualization of I/O devices ( 108 ). The device control module ( 206 ) also implements the I/O command and switching logic to perform graceful handling of the I/O commands and virtualized I/O devices between multiple host processors ( 104 ).

Claims (48)

1. A method comprising:

initializing one or more of at least one configuration register set, and at least one device register set for a I/O device, wherein each of the at least one configuration register set and the at least one device register set correspond to a host processor from amongst a plurality of host processors, and wherein each of the at least one configuration register set and the at least one device register set also correspond to the I/O device; and

providing the initialized configuration registers and the device registers to the plurality of host processors for virtualization of the I/O device:

assigning the I/O device to a first host processor from amongst the plurality of host processors to process a request from the first host processor;

queuing requests for the I/O device from host processors other than the first host processor amongst the plurality of host processors, wherein the queuing further comprises sending acknowledgements to the host processors in response to each of the requests; and

arbitrating the queued requests to choose a next request upon completion of a first request from the first host processor;

wherein the plurality of host processors identify the virtualized I/O device as a dedicated device.

2. The method as claimed in claim 1 , wherein the method further comprises:

parsing requests from the plurality of host processors for the I/O device to identify command boundaries; and

arbitrating between the requests from the plurality of host processors based at least on the identified command boundaries.

3. The method as claimed in claim 2 , wherein the arbitrating further comprises virtually disconnecting the I/O device from a host processor based on the identified command boundaries.

4. The method as claimed in claim 1 , wherein the method further comprises tapping at least one of a connect event, and a disconnect event associated with the I/O device for updating one or more of the at least one configuration register set, and the at least one device register set corresponding to the plurality of host processors.

5. The method as claimed in claim 4 , wherein the method further comprises sending the at least one of the connect event, and the disconnect event to at least one host processor from amongst the plurality of host processors.

6. A system comprising:

at least one device control module configured to implement at least one of configuration register set and at least one device register set for an I/O device corresponding to one or more virtual hierarchies, wherein the virtual hierarchies are associated with a plurality of host processors.

at least one command parser coupled to the at least one device control module configured to identify command boundaries of requests from the plurality of host processors based on packet header of the requests, wherein a request from a second host processor, from the plurality of host processors, is queued while command boundaries for a first host processor, from the plurality of host processors, are identified, wherein an acknowledgement is sent to the second host processor along with queuing of the request; and

a peripheral virtualization controller (PVC) coupled to the at least one device control module configured to:

control virtualization of the I/O device; and

control power state of at least one of the device control module and the I/O device based on the power state settings configured by the plurality of host processors.

7. The system as claimed in claim 6 , wherein the PVC is further configured to initialize at least one of the configuration registers and at least one of the device registers common for the virtual hierarchies.

8. The system as claimed in claim 6 , wherein the PVC is further configured to implement clock frequency of operation of the I/O device in accordance with each of the plurality of host processors.

9. The system as claimed in claim 6 , wherein the PVC is further configured to update the at least one device control module to switch the I/O device between the plurality of host processors.

10. The system as claimed in claim 6 , wherein the at least one device control module is further configured to switch the I/O device between the plurality of host processors based on the command boundaries.

11. The system as claimed in claim 6 , the system further includes a message handling module configured to:

support communication among the plurality of host processors; and

enable communication between the plurality of host processors and the PVC.

12. The system as claimed in claim 6 , wherein the PVC is further configured to act as a multi root PCI manager (MRPCIM).

13. The system as claimed in claim 6 , wherein the PVC is further configured to manage error conditions of the I/O devices among the plurality of host processors.

14. The system as claimed in claim 6 , wherein the PVC is one of a host processor from amongst the plurality of host processors.

15. The system as claimed in claim 6 , wherein the PVC is further configured to handle system level power management events based on active state of the host processors.

16. A system comprising:

a device control module configured to:

assign an I/O device to a first host processor from amongst the plurality of host processors to process a first request from the first host processor;

wherein the assigning includes associating a configuration register set and a device register set with the first host processor, from amongst at least one configuration register set and at least one device register set implemented for virtualization of the I/O device;

receive a second request from a second host processor from amongst the plurality of host processors for the virtualized I/O device;

queue the second request for the virtualized I/O device from the second host processor, wherein an acknowledgement is sent to the second host processor along with queuing of the second request;

arbitrate between the first request and the second request to select the second request based on the command boundary of the first request; and

assign the virtualized I/O device to the second host processor to process the second request, wherein the assigning includes associating another configuration register set and another device register set for the virtualized I/O device, with the second host processor, and the virtualized I/O device is simultaneously shared between the first host processor and the second host processor, and wherein the first host processor and the second host processor identify the virtualized I/O device as a dedicated device.

17. A system comprising:

a device control module configured to receive a first request for a virtualized I/O device from a first host processor from amongst the plurality of host processors;

process the first request for the virtualized I/O device from the first host processor;

receive a second request for the virtualized I/O device from a second host processor from amongst the plurality of host processors;

queue the second request for the virtualized I/O device from the second host processor, wherein an acknowledgement is sent to the second host processor along with queuing of the second request; and

assign the virtualized I/O device to the second host processor upon complete processing of the first request, wherein the virtualized I/O device is disconnected from the first host processor, wherein the assigning includes associating at least one of a configuration register set and a device register set corresponding to the virtualized I/O device with the second host processor and wherein the first host processor and the second host processor identify the virtualized I/O device as a dedicated device.

18. The system as claimed in claim 17 , wherein the assigning comprises:

sending a request to the first host processor to relinquish the control of the I/O device;

initiating a switch of the I/O device from the first host processor to the second host processor upon receiving an acknowledgement from the first host processor; and

providing an acknowledgement to the second host processor upon completion of the switching, wherein the acknowledgement is indicative of the assignment of the I/O device to the second host processor.

Assignments (6)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Feb 26, 2020
From: INEDA SYSTEMS, INC
To: SOCTRONICS
Reel/Frame 051937/0900 →
RELEASE OF SECURITY INTEREST Recorded Jan 17, 2020
From: SILICON VALLEY BANK
To: INEDA SYSTEMS, INC.
Reel/Frame 051546/0586 →
SECURITY INTEREST Recorded Feb 2, 2017
From: INEDA SYSTEMS, INC.
To: SILICON VALLEY BANK
Reel/Frame 041158/0665 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Dec 19, 2016
From: INEDA SYSTEMS PVT. LTD.
To: INEDA SYSTEMS INC.
Reel/Frame 040663/0014 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Oct 1, 2014
From: KANIGICHERLA, BALAJI; VOLETI, SIVA RAGHU RAM; TANDABOINA, KRISHNA MOHAN
To: INEDA SYSTEMS PVT. LTD
Reel/Frame 033865/0898 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Nov 27, 2013
From: KANIGICHERLA, BALAJI; VOLETI, SIVA RAGU RAM; TANDABOINA, KRISHNA MOHAN
To: INEDA SYSTEMS PVT. LTD
Reel/Frame 031689/0327 →
Priority Claims (1)
IN 2397/CHE/2010 · Aug 19, 2010 · national
Continuity (1)
Related Publication 20130151735A1 · Jun 13, 2013