IP Library Granted Patent US 9,210,796
Granted Patent B2
US 9,210,796 · App. 13/818,690 · Granted Dec 8, 2015

Light source mount

Inventor: David Benbassat (Ganey Tikva, IL)
Assignee: COLORCHIP (ISRAEL) LTD.
H05K1/02H01L23/49805H01L33/486H01L33/62H01S5/02236H01S5/02256H01L2924/0002
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Quick Facts
Patent No.
US 9,210,796
App. No.
13/818,690
Granted
Dec 8, 2015
Kind
B2
Abstract

A mount for a semiconductor device, the mount comprising: an insulating substrate having first and second parallel face surfaces, an edge surface that connects the parallel surfaces and having formed therein a recess having an opening on the first face surface; an electrically conductive plug seated in the recess and having a first exposed surface on or near the edge surface and a second exposed surface on or near the first face surface.

Claims (20)

1. A mount for a semiconductor device, the mount comprising:

an insulating substrate having first and second parallel face surfaces, an edge surface that connects the parallel surfaces and having formed therein a recess having an opening on the first face surface;

an electrically conductive plug seated in the recess and having a first exposed surface on or near the edge surface and a second exposed surface on or near the first face surface,

wherein the recess and the plug is characterized by a cross section having a dimension substantially parallel to the edge surface at a first distance from the edge surface that is smaller than a dimension of the cross section at a second, larger distance from the edge surface.

2. A mount according to claim 1 and comprising a conductive track formed on the first face surface that electrically contacts the exposed surface of the plug on the first face surface.

3. A mount according to claim 1 wherein the plug has a second surface exposed on or near the second face surface.

4. A mount according to claim 3 and comprising a conductive track formed on the second face surface that electrically contacts the exposed surface of the plug on the second face surface.

5. A mount according to claim 1 wherein the cross section comprises a first region and a second region connected by a neck region, the neck region being characterized by a relatively small width substantially parallel to the edge surface, and the first and second regions being characterized by relatively large widths parallel to the narrow width of the neck region.

6. A mount according to claim 5 wherein the cross section has a periphery coincident with a periphery of an area defined by two circles that partially overlap.

7. A mount according to claim 1 wherein the cross section has a trapezoidal shape.

8. A mount according to claim 1 wherein the semiconductor device comprises a laser diode.

9. A method of producing a mount for a semiconductor device, the method comprising:

forming a recess in a substrate formed from an electrically insulating material and having first and second parallel face surfaces, wherein the recess has an opening on the first face surface, and the recess is characterized by a cross section having a dimension parallel to and at a first distance from a line between the recesses in the pair of closely spaced rows to which the recess belongs that is smaller than a dimension of the cross section at a second, larger distance from the line;

filling the recess with an electrically conductive material; and

cutting the substrate to form an edge surface that connects the face surfaces and an exposed surface of the conductive material.

10. A method according to claim 9 wherein forming a recess comprises forming an array of rows and columns of recesses.

11. A method according to claim 10 wherein the rows comprise pairs of relatively closely spaced rows.

12. A method according to claim 9 wherein cutting the substrate comprises cutting the substrate along a line between a pair of closely spaced rows of recesses.

13. A method according to claim 9 , wherein the cross section comprises a first region and a second region connected by a neck region, the neck region being characterized by a relatively small width substantially parallel to the edge surface, and the first and second regions being characterized by relatively large widths parallel to the narrow width of the neck region.

14. A method according to claim 13 wherein the cross section has a periphery coincident with a periphery of an area defined by two circles that partially overlap.

Assignments (4)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jun 19, 2026
From: COLORCHIP (ISRAEL) LTD
To: COLORCHIP (ZHEJIANG) TECHNOLOGY CO., LTD
Reel/Frame 075014/0036 →
RELEASE OF SECURITY INTEREST Recorded Sep 5, 2019
From: SILICON VALLEY BANK
To: COLOR CHIP (ISRAEL) LTD.
Reel/Frame 050280/0756 →
SECURITY INTEREST Recorded Mar 16, 2017
From: COLOR CHIP (ISRAEL) LTD
To: SILICON VALLEY BANK
Reel/Frame 041600/0082 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Mar 19, 2013
From: BENBASSAT, DAVID
To: COLORCHIP (ISRAEL) LTD.
Reel/Frame 030037/0875 →
Continuity (2)
Provisional Application 61376281 · Aug 24, 2010
Related Publication 20130153281A1 · Jun 20, 2013