Method and apparatus for manufacturing three-dimensional-structure memory device

1. A method of manufacturing a memory device having a 3-dimensional structure, the method comprising:

alternately stacking one or more dielectric layers and one or more sacrificial layers on a substrate;

forming a through hole passing through the dielectric layers and the sacrificial layers;

forming a pattern filling the through hole;

forming an opening passing through the dielectric layers and the sacrificial layers; and

supplying an etchant through the opening to remove the sacrificial layers, the etchant comprising at least one selected from the group consisting of H 3 PO 4 , HF, and a buffered oxide etchant (BOE),

wherein the stacking of the dielectric layers includes supplying the substrate with one or more first gases selected from the group consisting of ethyl-based gas and methyl-based gas, and one or more second gases selected from the group consisting of SiH 4 , Si 2 H 6 , Si 3 H 8 , and Si 4 H 10 , to deposit a silicon carbon oxide (SiCO) layer, and

the stacking of the sacrificial layers includes supplying the substrate with one or more third gases selected from the group consisting of SiH 4 , Si 2 H 6 , Si 3 H 8 , Si 4 H 10 and dichloro silane (SiCl 2 H 2 ), and ammonia-based gas, to deposit a silicon nitride layer, and

wherein the sacrificial layer has an etch rate that is about 5 times to about 300 times greater than that of the dielectric layer.

2. The method of claim 1 , wherein the dielectric layer and the sacrificial layer have an etch selectivity with respect to the etchant.

3. The method of claim 1 , wherein the ammonia-based gas comprises NH 3 .

4. The method of claim 1 , wherein the substrate is maintained at a temperature ranging from about 300° C. to about 790° C. and a process pressure ranging from about 10 mTorr to about 250 Torr, during a process in which silane gas and a reaction gas are supplied in a chamber.

5. The method of claim 1 , wherein the silicon carbon oxide (SiCO) layer and the silicon nitride layer are different in thickness.

6. The method of claim 1 , wherein the alternately stacking of the dielectric layers and the sacrificial layers comprises pressing an edge of the substrate with an edge ring.

7. The method of claim 6 , wherein the edge of the substrate has a width ranging from about 0.5 mm to about 3 mm inward from a boundary of the substrate.

8. The method of claim 6 , wherein the edge ring is formed of ceramic.

9. A method of manufacturing a memory device having a 3-dimensional structure, the method comprising:

alternately stacking one or more dielectric layers and one or more sacrificial layers on a substrate;

forming a through hole passing through the dielectric layers and the sacrificial layers;

forming a pattern filling the through hole;

forming an opening passing through the dielectric layers and the sacrificial layers; and

supplying an etchant through the opening to remove the sacrificial layers, the etchant comprising at least one selected from the group consisting of H 3 PO 4 , HF, and a buffered oxide etchant (BOE),

wherein the stacking of the dielectric layers includes supplying the substrate with one or more first gases selected from the group consisting of ethyl-based gas and methyl-based gas, and one or more second gases selected from the group consisting of SiH 4 , Si 2 H 6 , Si 3 H 8 , and Si 4 H 10 , to deposit a silicon carbon oxide (SiCO) layer, and

the stacking of the sacrificial layers includes supplying the substrate with one or more third gases selected from the group consisting of SiH 4 , Si 2 H 6 , Si 3 H 8 , Si 4 H 10 and dichloro silane (SiCl 2 H 2 ), ammonia-based gas, and one or more fourth gases selected from the group consisting of B 2 H 6 and PH 3 , to deposit a silicon nitride layer in which boron or phosphorus is implanted, and

wherein the sacrificial layer has an etch rate that is about 5 times to about 300 times greater than that of the dielectric layer.