IP Library Granted Patent US 9,012,886
Granted Patent B2
US 9,012,886 · App. 13/826,787 · Granted Apr 21, 2015

Semiconductor light emitting device

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Quick Facts
Patent No.
US 9,012,886
App. No.
13/826,787
Granted
Apr 21, 2015
Kind
B2
Abstract

According to one embodiment, a semiconductor light emitting device includes: a first semiconductor layer; a second semiconductor layer; and a light emitting layer provided between the first and the second semiconductor layers. The first semiconductor layer includes a nitride semiconductor, and is of an n-type. The second semiconductor layer includes a nitride semiconductor, and is of a p-type. The light emitting layer includes: a first well layer; a second well layer provided between the first well layer and the second semiconductor layer; a first barrier layer provided between the first and the second well layers; and a first Al containing layer contacting the second well layer between the first barrier layer and the second well layer and containing layer containing Al x1 Ga 1-x1 N (0.1≦x 1 ≦0.35).

Claims (51)

1. A semiconductor light emitting device comprising:

a first semiconductor layer including a nitride semiconductor, the first semiconductor layer being of an n-type;

a second semiconductor layer including a nitride semiconductor, the second semiconductor layer being of a p-type; and

a light emitting layer provided between the first semiconductor layer and the second semiconductor layer, the light emitting layer including:

a first well layer including a nitride semiconductor;

a second well layer provided between the first well layer and the second semiconductor layer and including a nitride semiconductor;

a first barrier layer provided between the first well layer and the second well layer and including a nitride semiconductor, the first barrier layer directly contacting the first well layer, a band gap energy of the first barrier layer being greater than a band gap energy of the first well layer and a band gap energy of the second well layer; and

a first Al containing layer provided between the first barrier layer and the second well layer, the first Al containing layer directly contacting the first barrier layer and the second well layer, and the first Al containing layer containing Al x1 Ga 1-x1 N (0.1≦x 1 ≦0.35),

wherein the first barrier layer includes a first n-side layer and a first p-side layer provided between the first n-side layer and the first Al containing layer, and

an Al composition ratio of the first p-side layer is less than an Al composition ratio of the first Al containing layer.

2. The device according to claim 1 , wherein a thickness of the first Al containing layer is 0.5 nanometer or more and 2.5 nanometers or less.

3. The device according to claim 1 , wherein the second well layer includes a first portion containing In p21 Ga 1-p21 N (0.1<p 21 ≦0.4).

4. The device according to claim 3 , wherein the second well layer further includes a second portion provided between the first portion and the second semiconductor layer and containing In p22 Ga 1-p22 N (0<p 22 <p 21 ).

5. The device according to claim 4 , wherein the second well layer further includes a third portion provided between the first portion and the first Al containing layer and containing In p23 Ga 1-p23 N (0<p 23 <p 21 ).

6. The device according to claim 3 , wherein a thickness of the first portion is 0.5 nanometer or more and 2 nanometers or less.

7. The device according to claim 3 , wherein the first barrier layer includes

the first n-side layer contacting the first well layer and containing Al q11 In r11 Ga 1-q11-r11 N (0≦q 11 <1, 0≦r 11 <1, 0≦q 11 +r 11 ≦1, and r 11 <p 21 ), a band gap energy of the first n-side layer being greater than the band gap energy of the first portion, and

the first p-side layer provided between the first n-side layer and the second semiconductor layer and containing Al q12 In r12 Ga 1-q12-r12 N (0≦q 12 <1, 0≦r 12 <1, 0≦q 12 +r 12 ≦1, q 12 <q 11 , and r 12 <p 21 ), a band gap energy of the first p-side layer being greater than the band gap energy of the first portion.

8. The device according to claim 7 , wherein

a thickness of the first n-side layer is 0.5 nanometer or more and 5 nanometers or less, and

a thickness of the first p-side layer is 0.5 nanometer or more and 30 nanometers or less.

9. The device according to claim 3 , wherein the light emitting layer further includes a second barrier layer provided between the second well layer and the second semiconductor layer, and

the second barrier layer includes

a second n-side layer contacting the second well layer and containing Al q21 In r21 Ga 1-q21-r21 N (0≦q 21 <1, 0≦r 21 <1, 0≦q 21 +r 21 ≦1, and r 21 <p 21 ), a band gap energy of the second n-side layer being greater than the band gap energy of the first portion, and

a second p-side layer provided between the second n-side layer and the second semiconductor layer and containing Al q22 In r22 Ga 1-q22-r22 N (0≦q 22 <1, 0≦r 22 <1, 0≦q 22 +r 22 ≦1, q 22 <q 21 , and r 22 <p 21 ), a band gap energy of the second p-side layer being greater than the band gap energy of the first portion.

10. The device according to claim 9 , wherein

a thickness of the second n-side layer is 0.5 nanometer or more and 5 nanometers or less, and

a thickness of the second p-side layer is 0.5 nanometer or more and 30 nanometers or less.

11. The device according to claim 1 , wherein the second semiconductor layer is disposed on a [0001] direction side of the first semiconductor layer.

12. The device according to claim 1 , wherein a major surface of the first semiconductor layer is a c-plane.

13. The device according to claim 3 , wherein the light emitting layer further includes

a third well layer provided between the second well layer and the second semiconductor layer and including a nitride semiconductor,

a second barrier layer provided between the second well layer and the third well layer and including a nitride semiconductor, a band gap energy of the second barrier layer being greater than a band gap energy of the second well layer and a band gap energy of the third well layer, and

a second Al containing layer contacting the third well layer between the second barrier layer and the third well layer and containing Al x2 Ga 1-x2 N (0.1≦x 2 ≦0.35).

14. The device according to claim 13 , wherein a thickness of the second Al containing layer is 0.5 nanometer or more and 2.5 nanometers or less.

15. The device according to claim 13 , wherein the third well layer includes a first portion of the third well layer containing In p31 Ga 1-p31 N (0.1<p 31 ≦0.4).

16. The device according to claim 15 , wherein the third well layer further includes

a second portion of a third well layer provided between the first portion of the third well layer and the second semiconductor layer and containing In p32 Ga 1-p32 N (0<p 32 <p 31 ), and

a third portion of the third well layer provided between the first portion of the third well layer and the first semiconductor layer and containing In p33 Ga 1-p33 N (0<p 33 <p 31 ).

17. The device according to claim 15 , wherein a thickness of the first portion of the third well layer is 1 nanometer or more and 2 nanometers or less.

18. The device according to claim 1 , wherein the light emitting layer further includes

an n-side barrier layer provided between the first well layer and the first semiconductor layer and including a nitride semiconductor, a band gap energy of the n-side barrier layer being greater than a band gap energy of the first well layer and a band gap energy of the second well layer, and

an n-side Al containing layer contacting the first well layer between the n-side barrier layer and the first well layer and containing Al xn Ga 1-xn N (0.1≦xn≦0.35).

19. The device according to claim 1 , further comprising a p-side Al containing layer provided between the light emitting layer and the second semiconductor layer and including a nitride semiconductor containing Al, a band gap energy of the p-side Al containing layer being greater than a band gap energy of the first barrier layer.

20. The device according to claim 1 , wherein a peak wavelength of light emitted from the light emitting layer is 450 nanometers or more and 670 nanometers or less.

21. The device according to claim 1 , wherein a thickness of the first barrier layer is 5 nanometer or more and 30 nanometers or less.

22. The device according to claim 11 , wherein a thickness of the first Al containing layer is 0.5 nanometer or more and 2.5 nanometers or less.

23. The device according to claim 22 , wherein the second well layer includes a first portion containing In p21 Ga 1-p21 N (0.1<p 21 ≦0.4).

24. The device according to claim 23 , wherein a peak wavelength of light emitted from the light emitting layer is 450 nanometers or more and 670 nanometers or less.

25. The device according to claim 24 , wherein a thickness of the first barrier layer is 5 nanometer or more and 30 nanometers or less.

26. The device according to claim 1 , wherein a peak wavelength of light emitted from the light emitting layer is 400 nanometers or more and 670 nanometers or less.

Assignments (3)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Apr 6, 2020
From: TOSHIBA ELECTRONIC DEVICES & STORAGE CORPORATION
To: SEOUL SEMICONDUCTOR CO., LTD.
Reel/Frame 052316/0044 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jan 24, 2020
From: KABUSHIKI KAISHA TOSHIBA
To: TOSHIBA ELECTRONIC DEVICES AND STORAGE CORPORATION
Reel/Frame 051691/0442 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Mar 14, 2013
From: HWANG, JONGIL; SAITO, SHINJI; HASHIMOTO, REI; NUNOUE, SHINYA
To: KABUSHIKI KAISHA TOSHIBA
Reel/Frame 030002/0061 →