Compensation for temperature dependence of bit line resistance
Techniques for sensing the threshold voltage of a memory cell during reading and verify operations by compensating for changes, including temperature-based changes, in the resistance of a bit line or other control line. A memory cell being sensed is in a block in a memory array and the block is in a group of blocks. A portion of the bit line extends between the group of blocks and a sense component and has a resistance which is based on the length/distance and the temperature. Various parameters can be varied with temperature and the group of blocks to provide the compensation, including bit line voltage, selected word line voltage, source line voltage, sense time and/or sense current or voltage.
1. A method for performing a sense operation in a memory device, comprising:
determining a block in which a non-volatile storage element is located, wherein the block is among a plurality of blocks, a bit line extends from a sense component to each of the plurality of blocks, the bit line is in communication with a drain of the non-volatile storage element, the plurality of blocks are arranged in a plurality of groups, and groups of the plurality of groups have unequal numbers of adjacent blocks from among the plurality of blocks; and
sensing a state of the non-volatile storage element while compensating for a distance-based resistance and a temperature-based resistance of the bit line, the distance-based resistance is a function of a first distance of the bit line between the sense component and the block in which the non-volatile storage element is located, and the temperature-based resistance is a function of a temperature of the memory device and the first distance, wherein the compensating comprises applying a bit line voltage on the bit line, the bit line voltage has a rate of increase per degree C. of temperature which is relatively higher when the first distance is relatively greater, and the distance-based resistance and the temperature-based resistance are compensated for based on the group in which the non-volatile storage element is arranged.
a bit line which extends from the sense component to each of the plurality of blocks, the bit line is in communication with a drain of the non-volatile storage element, the bit line comprises a segment which extends in the bit line direction, and a vertical segment which is connected to the sense component and the segment which extends in the bit line direction;
a selected word line connected to a control gate of the selected non-volatile storage element; and
a control circuit, the control circuit is configured to perform a sense operation for the selected non-volatile storage element, the sense operation provides compensation for a distance-based resistance and a temperature-based resistance of the bit line, the distance-based resistance is a function of a first distance of the bit line between the sense component and the block in which the non-volatile storage element is located, and the temperature-based resistance is a function of a temperature of the memory device and the first distance, wherein the control circuit, to provide the compensation, is configured to apply a control gate voltage to the control gate of the non-volatile storage element during the sense operation, the control gate voltage has a rate of decrease per degree C. of temperature which is relatively higher when the first distance is relatively smaller, and the first distance comprises a distance of the vertical segment and a distance of the segment which extends in the bit line direction.
2. The method of claim 1 , wherein:
the applying the bit line voltage comprises providing a control signal to one adjustable resistor to provide a resistance which is a function of the first distance and providing a control signal to another adjustable resistor to provide a resistance which is a function of the first distance and of the temperature; and
the one adjustable resistor is in series with the another adjustable resistor in a circuit which applies a voltage to a clamping transistor; and
the clamping transistor clamps the bit line voltage.
3. The method of claim 2 , wherein:
an additional resistor is in series with the one adjustable resistor and the another adjustable resistor in the circuit; and
the additional resistor has a reference resistance which is not based on the temperature and is not based on the first distance.
4. The method of claim 3 , wherein:
the reference resistance is appropriate for a reference condition comprising a reference location of one block of the plurality of blocks and a reference temperature; and
the one adjustable resistor and the another adjustable resistor have a resistance of zero when the block in which the non-volatile storage element is located is the one block and the temperature of the memory device is the reference temperature.
5. The method of claim 1 , wherein:
a number of blocks in each group of the plurality of groups becomes progressively smaller moving away from or toward the sense component.
6. The method of claim 1 , wherein:
the plurality of blocks are arranged on a substrate in a bit line direction of the memory device;
each block of the plurality of blocks comprises a multi-layer stack in which vertical columns of memory cells are arranged;
the bit line comprises a vertical segment and a segment which extends in the bit line direction; and
the first distance comprises a distance of the vertical segment and a distance of the segment which extends in the bit line direction.
7. The method of claim 6 , wherein:
the sense component is on the substrate; and
the vertical segment is connected to the sense component and the segment which extends in the bit line direction.
8. The method of claim 7 , wherein:
the non-volatile storage element is in a NAND string;
the bit line comprises a vertical portion between the bit line and a drain end of the NAND string; and
the first distance comprises a distance of the vertical portion.