Semiconductor memory device, operating method thereof, and memory system including the same

1. An operating method of a semiconductor memory device having plural memory strings each of which has plural memory cells defined by word lines surrounding a vertical channel layer at different levels from a semiconductor substrate, the vertical channel layer connected between a bit line and a common source line, the method comprising:

supplying a first voltage to a selected bit line where a selected memory cell among the memory cells is connected and a second voltage, which is higher than the first voltage, to an unselected bit line;

supplying a third voltage to a selected drain select line where the selected memory cell is connected and a fourth voltage, which is lower than the third voltage, to an unselected drain select line; and

supplying a fifth voltage to a selected word line where the selected memory cell is connected and a sixth voltage, which is lower than the fifth voltage, to unselected word lines, for a program operation.

2. The method of claim 1 , wherein the first voltage is at substantially the same level as the fourth voltage.

3. The method of claim 1 , wherein the second voltage at substantially the same level as the third voltage.

4. The method of claim 1 , wherein the fifth voltage is higher than a program voltage which is supplied to the selected word line in the program operation.

5. The method of claim 1 , wherein the sixth voltage is higher than a pass voltage which is supplied to the unselected word lines in the program operation.

6. The method of claim 1 , wherein the step of supplying the fifth voltage and the sixth voltage comprises:

supplying the sixth voltage to the selected word line and the unselected word lines; and

increasing a voltage level of the selected word line to a level of the fifth voltage.

7. The method of claim 1 , wherein the first voltage is higher than a ground voltage.

8. A semiconductor memory device, comprising:

a memory block including plural memory strings each of which has plural memory cells defined by word lines surrounding a vertical channel layer at different levels from a semiconductor substrate, wherein the vertical channel layer is connected between a bit line and a common source line; and

a peripheral circuit configured to supply a first voltage to a selected bit line to which selected memory cells are connected, a second voltage higher than the first voltage to an unselected bit line, a third voltage to a selected drain select line to which the selected memory cell is connected, a fourth voltage lower than the third voltage to an unselected drain select line, a fifth voltage to a selected word line to which the selected memory cell is connected, and a sixth voltage lower than the fifth voltage to unselected word lines, during a program operation.

9. The semiconductor memory device of claim 8 , wherein the first voltage is at substantially the same level as the fourth voltage.

10. The semiconductor memory device of claim 8 , wherein the second voltage is at substantially the same level as the third voltage.

11. The semiconductor memory device of claim 8 , wherein the fifth voltage is higher than a program voltage which is supplied to the selected word line in the program operation.

12. The semiconductor memory device of claim 8 , wherein the sixth voltage is higher than a pass voltage which is supplied to the unselected word lines in the program operation.

13. The semiconductor memory device of claim 8 , wherein the peripheral circuit supplies the sixth voltage to the selected word line and the unselected word lines, and increases a voltage level of the selected word line to a level of the fifth voltage.

14. The semiconductor memory device of claim 8 , wherein the first voltage is higher than a ground voltage.

15. A semiconductor memory device, comprising:

a memory block including word lines surrounding a vertical channel layer connected between one of bit lines and a common source line at different levels from a semiconductor substrate, and including plural memory strings each of which has plural memory cells formed at areas at which the word lines surround the vertical channel layer;

a page buffer connected to the memory block through the bit lines and configured to supply a first voltage to a selected bit line to which selected memory cells are connected and a second voltage higher than the first voltage to an unselected bit line during a program operation; and

a voltage supply connected to the memory block through the word lines and select lines, and configured to supply a third voltage to a selected drain select line to which the selected memory cell is connected, a fourth voltage lower than the third voltage to an unselected drain select line, a fifth voltage to a selected word line to which the selected memory cell is connected, and a sixth voltage lower than the fifth voltage to unselected word lines, during the program operation.

16. The device of claim 15 , wherein the first voltage is at substantially the same level as the fourth voltage.

17. The device of claim 15 , wherein the second voltage is at substantially the same level as the third voltage.

18. The device of claim 15 , wherein the fifth voltage is higher than a program voltage which is supplied to the selected word line in the program operation.

19. The device of claim 15 , the sixth voltage is higher than a pass voltage which is supplied to the unselected word lines in the program operation.

20. The device of claim 15 , wherein the voltage supply applies the sixth voltage to the selected word line and the unselected word lines, and increases a voltage level of the selected word line to a level of the fifth voltage.