IP Library Granted Patent US 8,916,422
Granted Patent B2
US 8,916,422 · App. 13/831,964 · Granted Dec 23, 2014

Semiconductor packages and methods of packaging semiconductor devices

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Quick Facts
Patent No.
US 8,916,422
App. No.
13/831,964
Granted
Dec 23, 2014
Kind
B2
Abstract

Package substrate, semiconductor packages and methods for forming a semiconductor package are presented. The package substrate includes a base substrate having first and second major surfaces and a plurality of via contacts extending through the first to the second major surfaces of the base substrate. A first conductive layer having a plurality of openings is disposed over the first surface of the base substrate and via contacts. The openings are configured to match conductive trace layout of the package substrate. Conductive traces are disposed over the first conductive layer. The conductive traces are directly coupled to the via contacts through some of the openings of the first conductive layer.

Claims (58)

1. A method for forming a semiconductor package comprising:

providing a conductive carrier having first and second surfaces;

forming a first conductive layer having first and second type openings over the first surface of the conductive carrier;

forming conductive traces over the first conductive layer;

mounting a die on the first surface of the conductive carrier, the die is coupled to the conductive traces;

encapsulating the die with a cap;

processing the second surface of the conductive carrier to form via contacts of a package substrate, wherein the conductive traces are directly coupled to the via contacts through the first type openings of the first conductive layer; and

forming an insulating layer filling spaces between the via contacts to form a base substrate of the package substrate.

2. The method of claim 1 wherein forming the first conductive layer comprises:

providing a first patterned mask layer over the first surface of the conductive carrier;

plating a first conductive material over exposed portions of the conductive carrier; and

removing the first patterned mask layer to form at least the first type openings.

3. The method of claim 1 wherein forming the conductive traces comprises:

forming a second patterned mask over the first conductive layer;

plating a second conductive material over exposed portions of the first conductive layer not covered by the second patterned mask.

4. The method of claim 3 comprising removing portions of the first conductive layer to form the second type openings using the conductive traces as an etch mask.

5. The method of claim 1 wherein forming the first conductive layer comprises:

providing a first patterned mask layer over the first surface of the conductive carrier;

plating a first conductive material over exposed portions of the conductive carrier; and

removing the first patterned mask layer to form the first and second type openings, wherein the first type openings define locations under which via contacts are formed while the second type openings define locations under which no via contacts are formed.

6. The method of claim 5 wherein forming the conductive traces comprises:

blanket plating a second conductive layer over the first conductive layer, wherein the second conductive layer comprises first planar portions over a first surface of the first conductive layer and second recessed portions lining the second type openings of the first conductive layer; and wherein

processing the second surface of the conductive carrier to form via contacts comprises an etch which simultaneously remove portions of the recessed portions of the second conductive layer to define the conductive traces.

7. The method of claim 6 wherein:

the conductive carrier and the second conductive layer comprise a second conductive material; and

the first conductive layer comprises a first conductive material which is different than the second conductive material.

8. The method of claim 7 wherein the second conductive material comprises copper and the first conductive material comprises nickel.

9. The method of claim 6 wherein the base substrate includes first and second surfaces, wherein the first surface of the base substrate include protrusions which partially fill the second type openings of the first conductive layer.

10. The method of claim 1 comprising forming contact pads over portions of the conductive traces, wherein the die is coupled to the contact pads.

11. The method of claim 1 wherein the conductive carrier comprises a thickness which is substantially the same as thickness of the via contacts to be formed.

12. The method of claim 11 comprising:

providing a support carrier prepared with an adhesive layer over a first surface of the support carrier; and

attaching the conductive carrier to the support carrier prior to forming the via contacts.

13. The method of claim 5 wherein forming the conductive traces comprises blanket plating a second conductive layer over the first conductive layer, wherein the second conductive layer comprises first planar portions over a first surface of the first conductive layer and second recessed portions lining the second type openings of the first conductive layer.

14. The method of claim 13 comprising forming a dielectric layer over the second conductive layer after blanket plating the second conductive layer.

15. The method of claim 14 wherein the dielectric layer comprises a solder mask.

16. The method of claim 14 comprising:

removing portions of the dielectric layer to form a plurality of openings in the dielectric layer exposing portions of top surface of the second conductive layer; and

forming contact pads over exposed portions of the second conductive layer.

17. The method of claim 14 wherein processing the second surface of the conductive carrier to form via contacts comprises:

thinning the conductive carrier to a desired via contact thickness; and

patterning the thinned conductive carrier to remove portions of the conductive carrier to form the via contacts.

18. The method of claim 17 wherein:

the conductive carrier and the second conductive layer comprise a second conductive material; and

the first conductive layer comprises a first conductive material which is different than the second conductive material.

19. The method of claim 18 wherein patterning the thinned conductive carrier comprises an etch which simultaneously remove portions of the recessed portions of the second conductive layer to define the conductive traces, and wherein the first conductive layer serves as an etch stop layer during formation of the via contacts.

20. The method of claim 19 wherein forming the insulating layer also partially fills the second type openings of the first conductive layer.

21. The method of claim 6 comprising:

removing portions of the dielectric layer to form a plurality of openings in the dielectric layer exposing portions of top surface of the second conductive layer;

forming contact pads over exposed portions of the second conductive layer; and

removing portions of the dielectric layer to exposed second recessed portions of the second conductive layer.

22. The method of claim 2 comprising:

removing portions of the dielectric layer to form a plurality of openings in the dielectric layer exposing portions of top surface of the second conductive layer;

forming contact pads over exposed portions of the second conductive layer; and

removing remaining portions of the dielectric layer except for portions of the dielectric layer under the die.

23. The method of claim 1 comprising:

providing a support carrier prepared with an adhesive layer over a first surface of the support carrier; and

attaching the conductive carrier to the support carrier after forming the conductive traces over the first conductive layer and prior to forming the via contacts.

Assignments (4)
CORRECTIVE ASSIGNMENT TO CORRECT THE INCLUDE PATENT NUMBER 8816482 PREVIOUSLY RECORDED AT REEL: 039885 FRAME: 0541. ASSIGNOR(S) HEREBY CONFIRMS THE ASSIGNMENT. Recorded Sep 25, 2017
From: UNITED TEST AND ASSEMBLY CENTER LIMITED
To: UTAC HEADQUARTERS PTE. LTD.
Reel/Frame 043979/0820 →
CORRECTIVE ASSIGNMENT TO CORRECT THE TO ADD THE ANNEX A AND THE ANNEX B WHICH WAS INADVERTENTLY LEFTOUT IN THE ORIGINAL ASSIGNMENT DOCUMENT PREVIOUSLY RECORDED ON REEL 037959 FRAME 0822. ASSIGNOR(S) HEREBY CONFIRMS THE ASSIGNMENT. Recorded Jul 8, 2016
From: UNITED TEST AND ASSEMBLY CENTER LIMITED
To: UTAC HEADQUARTERS PTE. LTD.
Reel/Frame 039885/0541 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Mar 1, 2016
From: UNITED TEST AND ASSEMBLY CENTER LIMITED
To: UTAC HEADQUARTERS PTE. LTD.
Reel/Frame 037959/0822 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Mar 15, 2013
From: WANG, CHUEN KHIANG
To: UNITED TEST AND ASSEMBLY CENTER LTD.
Reel/Frame 030008/0660 →