IP Library Granted Patent US 8,952,493
Granted Patent B2
US 8,952,493 · App. 13/832,761 · Granted Feb 10, 2015

Memory cell device and method of manufacture

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Quick Facts
Patent No.
US 8,952,493
App. No.
13/832,761
Granted
Feb 10, 2015
Kind
B2
Abstract

According to one embodiment of the present invention, a solid state electrolyte memory cell includes a cathode, an anode and a solid state electrolyte. The anode includes an intercalating material and first metal species dispersed in the intercalating material.

Claims (29)

1. A memory cell, comprising:

an anode electrode comprising a layer of an inorganic intercalating material and at least a first metal species dispersed in the inorganic intercalating material;

a cathode electrode; and

a solid state electrolyte formed between the anode and cathode electrodes, wherein the solid state electrolyte is programmable between different resistance values by electric pulsing.

2. The memory cell of claim 1 , wherein:

the anode electrode comprises titanium.

3. The memory cell of claim 1 , wherein:

the anode electrode comprises copper.

4. The memory cell of claim 1 , wherein:

the anode electrode comprises copper and titanium.

5. The memory cell of claim 1 , wherein:

the layer of intercalating material has a thickness in the range of about 30 nm to 100 nm.

6. The memory cell of claim 1 , wherein:

the cathode electrode comprises titanium.

7. The memory cell of claim 1 , wherein:

the cathode electrode comprises a material selected from the group of: W, TiN, TiW, and TiA1N.

8. An integrated circuit device, comprising:

a plurality of memory cells, each memory cell comprising a cathode electrode, a solid electrolyte layer, and

an anode electrode that includes an inorganic intercalating material, and

a first metal species dispersed in the inorganic intercalating material; wherein

each memory cell is switchable between different resistance values by bipolar electric pulsing.

9. The integrated circuit device of claim 8 , wherein:

the anode electrode of each memory cell comprises titanium.

10. The integrated circuit device of claim 8 , wherein:

the anode electrode of each memory cell comprises copper.

11. The integrated circuit device of claim 8 , wherein:

the anode electrode of each memory cell comprises copper and titanium.

12. The integrated circuit device of claim 8 , wherein:

the memory cells are arranged between bit lines and word lines.

Assignments (4)
RELEASE OF SECURITY INTEREST Recorded Sep 24, 2019
From: OBSIDIAN AGENCY SERVICES, INC., AS COLLATERAL AGENT
To: ADESTO TECHNOLOGIES CORPORATION; ARTEMIS ACQUISITION LLC
Reel/Frame 050480/0836 →
RELEASE OF SECURITY INTEREST Recorded May 9, 2019
From: OPUS BANK
To: ADESTO TECHNOLOGIES CORPORATION; ARTEMIS ACQUISITION LLC
Reel/Frame 049125/0970 →
SECURITY INTEREST Recorded May 8, 2018
From: ADESTO TECHNOLOGIES CORPORATION; ARTEMIS ACQUISITION LLC
To: OBSIDIAN AGENCY SERVICES, INC., AS COLLATERAL AGENT
Reel/Frame 046105/0731 →
SECURITY INTEREST Recorded May 22, 2015
From: ADESTO TECHNOLOGIES CORPORATION; ARTEMIS ACQUISITION LLC
To: OPUS BANK
Reel/Frame 035754/0580 →