Differential voltage-mode buffer with current injection

1. A differential buffer, comprising:

delay circuitry configured to generate one or more pairs of complementary signals from a serial data stream;

first circuitry configured to generate a first end of a differential output signal, the first circuitry including:

first voltage-mode circuitry that is configurable using a first subset of the complementary signals to provide a first plurality of signal levels to a first subset of data pulses derived from the serial data stream; and

first current-mode circuitry comprising one or more first current sources that are configurable using a second subset of the complementary signals to inject current to or remove current from the first end of the differential output signal to provide a second plurality of signal levels to a second subset of the data pulses.

2. The differential buffer of claim 1 , further comprising second circuitry configured to generate a second end of the differential output signal, the second circuitry including:

second voltage-mode circuitry that is configurable using a third subset of the complementary signals to provide a third plurality of signal levels to a third subset of the data pulses corresponding to the first subset of data pulses; and

second current-mode circuitry comprising one or more second current sources that are configurable using a fourth subset of the complementary signals to inject current to or remove current from the second end of the differential output signal to provide a fourth plurality of signal levels to a fourth subset of the data pulses corresponding to the second subset of the data pulses.

3. The differential buffer of claim 2 , wherein the consecutive bits in the serial data stream correspond to a main cursor pulse, a post-cursor pulse, and a post-cursor2 pulse as specified by the DisplayPort standard.

4. The differential buffer of claim 1 , wherein the pairs of complementary signals correspond to consecutive data bits in the serial data stream.

5. The differential buffer of claim 1 , wherein the first voltage-mode circuitry comprises:

a first plurality of drivers;

a first plurality of series resistors each in series with an output of a corresponding one of the first plurality of drivers; and

first selection circuitry for selecting inputs for each of the first plurality of drivers from among the first subset of the complementary signals, thereby driving the outputs of a first subset of the first plurality of drivers high and the outputs of a second subset of the first plurality of drivers low, thereby configuring the first voltage divider.

6. The differential buffer of claim 1 , wherein the first current-mode circuitry comprises a first current-injecting current source, a first current-removing current source, and first selection circuitry for selectively connecting the first current-injecting current source and the first current-removing current source to the first end of the differential output signal.

7. The differential buffer of claim 1 , further comprising a complementary signal generator configured to generate a second end of the differential output signal using input from the first circuitry.

8. A transmitter circuit including the differential buffer of claim 1 as an output buffer, the transmitter being configured to transmit the differential output signal according to a serial interface standard.

9. The transmitter circuit of claim 8 wherein the serial interface standard is selected from the group including the DisplayPort standards, the HDMI standards, the Serial ATA standards, the PCI-E standards, or the USB standards.

10. A buffer, comprising:

delay circuitry configured to generate one or more control signals from a serial data stream;

voltage-mode circuitry that is configurable using a first subset of the control signals to provide a first plurality of signal levels of an output signal of the buffer to a first subset of data pulses derived from the serial data stream; and

current-mode circuitry comprising one or more current sources that are configurable using a second subset of the control signals to inject current to or remove current from the output signal to provide a second plurality of signal levels at the output signal to a second subset of the data pulses.

11. The buffer of claim 10 , wherein the output signal of the buffer is a differential signal.

12. The buffer of claim 10 , wherein the control signals correspond to consecutive data bits in the serial data stream.

13. The buffer of claim 12 , wherein the consecutive bits in the serial data stream correspond to a main cursor pulse, a post-cursor pulse, and a post-cursor2 pulse as specified by the DisplayPort standard.

14. A transmitter circuit including the buffer of claim 10 , the transmitter being configured to transmit the output signal according to a serial interface standard.

15. The transmitter circuit of claim 14 wherein the serial interface standard is selected from the group including the DisplayPort standards, the HDMI standards, the Serial ATA standards, the PCI-E standards, or the USB standards.

16. A method for generating a differential signal corresponding to a serial data stream, comprising:

generating one or more pairs of complementary signals from the serial data stream;

generate a first end of the differential signal by configuring first voltage-mode circuitry using a first subset of the complementary signals to provide a first plurality of signal levels to a first subset of data pulses derived from the serial data stream; and

configuring one or more first current sources using a second subset of the complementary signals to inject current to or remove current from the first end of the differential output signal to provide a second plurality of signal levels to a second subset of the data pulses.

17. The method of claim 16 , wherein the pairs of complementary signals correspond to consecutive data bits in the serial data stream.

18. The method of claim 17 , wherein the consecutive bits in the serial data stream correspond to a main cursor pulse, a post-cursor pulse, and a post-cursor2 pulse as specified by the DisplayPort standard.

19. The method of claim 16 , further comprising:

generating a second end of the differential by configuring second voltage-mode circuitry using a third subset of the complementary signals to provide a third plurality of signal levels to a third subset of the data pulses corresponding to the first subset of data pulses; and

configuring one or more second current sources using a fourth subset of the complementary signals to inject current to or remove current from the second end of the differential output signal to provide a fourth plurality of signal levels to a fourth subset of the data pulses corresponding to the second subset of the data pulses.

20. The method of claim 16 , further comprising generating a second end of the differential output signal using a complementary signal generator using input from circuitry generating the first end of the differential output signal.