Adaptive optimum CDR bandwidth estimation by using a kalman gain extractor
Exemplary embodiments of the present invention relate to a clock and data recovery (CDR) apparatus with adaptive optimum CDR bandwidth estimation by using a Kalman gain extractor. The Kalman gain extractor includes an off chip digital processor which receives a phase update information from the CDR outputs an estimated optimum Kalman gain obtained by extracting the standard deviation of step sizes of the accumulation jitter from the power spectral density (PSD) of the phase update information, and a on chip digital loop filter consists of a cyclic accumulator which accumulates the phase detector's output, a gain multiplier and a phase interpolator (or DCO) controller. The off chip digital processor includes a storage register, a fast Fourier transform (FFT) processor and an optimum Kalman gain estimator. The storage register stores the phase update information, from which the FFT processor extracts the PSD of the absolute input jitter. The optimum Kalman gain estimator calculates the optimum gain from the PSD of the accumulation jitter. The off chip digital processor may further include a gain calibrator to compensate for the variations in the transition density.
1. A clock and data recovery (CDR) apparatus with adaptive optimum CDR bandwidth estimation by using a Kalman gain extractor comprising:
a clock generator configured to provide frequency locked clocks to a digitally controlled phase rotator;
a bang-bang phase detector (BBPD); and
a Kalman gain extractor configured to estimate an optimum Kalman gain for a loop filter connected to the BBPD and the phase rotator, wherein the Kalman gain extractor includes,
an on-chip digital loop filter; and
an off-chip digital processor to receive phase update information from the CDR apparatus and output the optimum Kalman gain.
2. The CDR apparatus with adaptive optimum CDR bandwidth estimation by using a Kalman gain extractor of claim 1 , wherein the on-chip digital loop filter includes a cyclic accumulator, a gain multiplier and one of a phase interpolator controller and DCO controller.
3. The CDR apparatus with adaptive optimum CDR bandwidth estimation by using a Kalman gain extractor of claim 1 , wherein the off-chip digital processor outputs the optimum Kalman gain obtained by extracting a standard deviation of step sizes of an accumulation jitter from power spectral density (PSD) of the phase update information.
4. The CDR apparatus with adaptive optimum CDR bandwidth estimation by using a Kalman gain extractor of claim 1 , wherein the off-chip digital processor includes,
a storage register configured to store the phase update information; and
a fast Fourier transform (FFT) processor configured to extract PSD of an absolute input jitter from the phase update information.
5. The CDR apparatus with adaptive optimum CDR bandwidth estimation by using a Kalman gain extractor of claim 4 , wherein the off-chip digital processor further includes,
an optimum Kalman gain estimator configured to calculate the optimum Kalman gain from the PSD of an accumulation jitter.
6. The CDR apparatus with adaptive optimum CDR bandwidth estimation by using a Kalman gain extractor of claim 5 , wherein the off-chip digital processor further includes,
a gain calibrator configured to compensate for variations in transition density.
7. A clock and data recovery (CDR) apparatus with adaptive optimum CDR bandwidth estimation by using a Kalman gain extractor comprising:
a clock generator configured to provide frequency locked clocks to a digitally controlled phase rotator;
a bang-bang phase detector (BBPD); and
a Kalman gain extractor configured to estimate an optimum Kalman gain for a loop filter connected to the BBPD and the phase rotator, wherein the Kalman gain extractor includes,
an on-chip digital loop filter; and
an off-chip digital processor to receive phase update information from the CDR apparatus and output the optimum Kalman gain, and wherein the Kalman gain extractor includes,
a Kalman filter configured to find the optimum Kalman gain by minimizing a posterior MSE recursively.
8. A clock and data recovery (CDR) apparatus with adaptive optimum CDR bandwidth estimation by using a Kalman gain extractor comprising:
a clock generator configured to provide frequency locked clocks to a digitally controlled phase rotator;
a bang-bang phase detector (BBPD); and
a Kalman gain extractor configured to estimate an optimum Kalman gain for a loop filter connected to the BBPD and the phase rotator, wherein the Kalman gain extractor includes,
an on-chip digital loop filter; and
an off-chip digital processor to receive phase update information from the CDR apparatus and output the optimum Kalman gain, and wherein the BBPD includes a demultiplexer modeled by parallel BBPDs with a subsequent summation block.