Low-power CML-less transmitter architecture
Exemplary embodiments of the present invention relate to a low-power current mode logic (CML)-less transmitter architecture. A transmitter comprises a main multiplexer configured to generate a main data signal by multiplexing parallel main data signals retimed from a retimer for time margin between parallel input data signals and a multiphase clock signals from a clock distributor, a secondary multiplexer configured to generate a post data signal by multiplexing parallel post data signals retimed from the retimer, and a plurality of output drivers configured to generate a serial data signal by summing the main data signal and the post data signal.
1. A transmitter comprising:
a main multiplexer configured to generate a main data signal by multiplexing parallel signals and to output the main data signal, when two neighboring quarter phase clock signals among multiphase clock signals overlap, wherein the main multiplexer comprises a plurality of cascaded N-channel metal oxide semiconductor (NMOS) transistors and adjustable pseudo P-channel metal oxide semiconductor (pseudo-PMOS) loads and the cascaded NMOS transistors are driven by differential input data and the two neighboring quarter phase clock signals;
a secondary multiplexer configured to generate a post data signal by multiplexing the parallel signals and to output the post data signal when the two neighboring quarter phase clock signals overlap; and
a main driver and a post driver configured and arranged for receiving the main data signal and the post data signal, respectively,
wherein an output of the main driver associated with an input DIN[n] of the main driver is connected with an output of the post driver associated with a differential input /DIN[n−1] of the post driver to generate a first output /OUT, and an output of the main driver associated with an input /DIN[n] of the main driver is connected with an output of the post driver associated with a differential input DIN[n−1] of the post driver to generate a second output OUT,
wherein a pre-emphasized output signal is generated by summing the first output /OUT and the second output OUT.
2. The transmitter of claim 1 , further comprising:
a multiplexer configured to generate the parallel signals for the main multiplexer and the secondary multiplexer by multiplexing parallel input data signals.
3. The transmitter of claim 2 , further comprising:
a retimer configured to process retiming the parallel signals generated by the multiplexer for providing a timing margin between the parallel signals and the multiphase clock signals from a clock distributor.
4. The transmitter of claim 2 , wherein the multiplexer comprises a plurality of 5:1 multiplexers and a plurality of 2:1 multiplexers.
5. The transmitter of claim 1 , wherein a size of the cascaded NMOS transistors is determined based on required pre-emphasis tap weights for the channel loss compensation.
6. The transmitter of claim 5 , wherein the secondary multiplexer comprises a plurality of cascaded N-channel metal oxide semiconductor (NMOS) transistors, and
wherein a size of the cascaded NMOS transistors of the secondary multiplexer is smaller than the size of the cascaded NMOS transistors of the main multiplexer.
7. The transmitter of claim 1 , wherein an amount of pre-emphasis is controlled by adjusting the bias current of a post driver included in the plurality of output drivers.