Instruction boundary prediction for variable length instruction set
A system, processor, and method to predict with high accuracy and retain instruction boundaries for previously executed instructions in order to decode variable length instructions is disclosed. In at least one embodiment, a disclosed processor includes an instruction fetch unit, an instruction cache, a boundary byte predictor, and an instruction decoder. In some embodiments, the instruction fetch unit provides an instruction address and the instruction cache produces an instruction tag and instruction cache content corresponding to the instruction address. The instruction decoder, in some embodiments, includes boundary byte logic to determine an instruction boundary in the instruction cache content.
1. A processor, comprising:
an instruction fetch unit to provide an instruction address;
an instruction cache to produce an instruction tag and instruction cache content corresponding to the instruction address;
a boundary byte predictor to receive the instruction tag and generate a prediction vector to indicate a prediction of a first byte of an instruction, the prediction vector including a bit corresponding to each byte in a group of instruction cache content bytes, wherein the boundary byte predictor includes an array of filters, and further wherein each filter is to produce a bit value based on a hash of the instruction tag; and
an instruction decoder including boundary byte logic to determine an instruction boundary in the instruction cache content, wherein the boundary byte logic is to form an initial prediction of the first byte of the instruction based on the prediction vector, and to decode the instruction beginning with the predicted first byte of the instruction.
2. The processor of claim 1 , wherein the group of instruction cache content bytes includes each byte in the content associated with the instruction tag.
3. The processor of claim 1 , wherein the group of instruction cache content bytes includes a subset of the content associated with the instruction tag.
4. The processor of claim 3 , wherein the boundary byte predictor is to receive a subset input indicative of the subset of the content.
5. The processor of claim 4 , wherein the subset input is indicative of an instruction pointer value.
6. The processor of claim 1 , wherein each filter in the array of filters is to generate multiple hashed outputs of the instruction tag and determine the bit value based on the multiple hashed outputs.
7. A computer system, comprising:
a processor, the processor comprising:
an instruction fetch unit to provide an instruction address;
an instruction cache to produce an instruction tag and instruction cache content corresponding to the instruction address;
a boundary byte predictor to receive the instruction tag and generate a prediction vector including a bit corresponding to each byte in a group of instruction cache content bytes, the prediction vector to indicate a prediction of a first byte of an instruction, wherein the boundary byte predictor includes an array of filters, and further wherein each filter is to produce a bit value based on a hash of the instruction tag; and
an instruction decoder including boundary byte logic to determine an instruction boundary in the instruction cache content, wherein the boundary byte logic is to form an initial prediction of a boundary byte of the instruction based on the prediction vector and the instruction decoder is to decode the instruction based on the initial prediction;
an I/O bridge to provide an interface for an I/O device; and
a system memory, accessible to the processor.
8. The system of claim 7 , wherein the processor includes a plurality of processing cores, and further wherein each of the plurality of processing cores includes a boundary byte predictor.
9. The system of claim 7 , wherein the group of instruction cache content bytes includes each byte in the content associated with the instruction tag.
10. The system of claim 7 , wherein the group of instruction cache content bytes includes a subset of the content associated with the instruction tag.
11. The system of claim 10 , wherein the boundary byte predictor is to receive a subset input indicative of the subset of content.
12. The system of claim 11 , wherein the subset input is indicative of an instruction pointer value.
13. The system of claim 7 , wherein each filter in the array of filters is to generate multiple hashed outputs of the instruction tag and determine the bit value based on the multiple hashed outputs.
14. A method, comprising:
providing an instruction tag to a predictor comprising an array of filters, wherein each filter is to produce a bit value based on a hash of the instruction tag;
providing instruction cache content corresponding to the instruction address to an instruction decoder;
receiving a prediction vector including a bit corresponding to each byte in a group of instruction cache content bytes;
determining, from an initial prediction of a boundary byte based on the prediction vector, an instruction boundary in the instruction cache content; and
decoding an instruction in the instruction cache content beginning at the determined instruction boundary.
15. The method of claim 14 , wherein the array of filters includes a predictor for each byte in the cache content.
16. The method of claim 15 , further comprising: providing subset bits to the predictor, wherein the subset bits are indicative of a subset of the instruction cache content bytes.
17. The method of claim 16 , further comprising: providing the subset bits to the instruction decoder with the predictor vector.
18. The method of claim 16 , further comprising: generating the subset bits based on an instruction pointer value.
19. The method of claim 14 , wherein the array of filters comprises an array of bloom filters.